In the field of embedded systems, NOR flash and NAND flash, as storage devices, should be familiar to everyone. The interface of early NOR flash was in the form of parallel port, that is, the data line and address line were set side by side in the IC pins. However, due to the fact that parallel port NOR flash of different capacities are not hardware compatible (the number of data lines and address lines is different), and the package is relatively large, occupying a large space on the PCB board, it was gradually replaced by SPI (serial interface) NOR flash. SPI NOR flash can achieve pin compatibility with NOR flash of different capacities, and adopts a smaller package form (SOP8 is more typical), and quickly replaced parallel port NOR flash to become the mainstream of the market. So much so that many people now directly refer to NOR flash as SPI flash. For NAND flash, since the address data line is multiplexed and the interface standard is unified (X 8 bit or X 16 bit), there is basically no problem in compatibility with different capacities. Therefore, this package and interface form have been used for many years. In recent years, with the increasing demand for product miniaturization and the increasing requirements for solution costs, SPI NAND flash has gradually entered the eyes of many engineers. If the SPI NAND flash solution is adopted, the main control (MCU) does not need to have a controller with traditional NAND, but only needs an SPI interface, which can reduce the cost of the main control. In addition, the packaging form of SPI NAND flash mostly adopts WSON packaging, which is much smaller than the traditional NAND flash TSOP packaging, which fully saves the space of the PCB board and the number of pins, thereby reducing the size and number of layers of the PCB, which not only meets the demand for miniaturization but also reduces the cost of the product. From the above, we have learned about the advantages of SPI NAND flash. So, is its performance lower than that of traditional NAND flash? We take the 1Gb SPI NAND flash model ATO25D1GA of South Korea's ATO solution as an example. It is the world's first single-wafer SPI NAND flash. SPI NAND flash is essentially a NAND flash + SPI controller. In order to provide customers with stable and reliable flash chips and ensure the consistency of user program codes, ATO solution designs NAND flash and SPI controller on a single wafer, thus ensuring that all SPI NAND flash shipped by ATO solution have consistent controllers. When customers program SPI, they will not encounter the problem of driver adjustment due to different controllers. In addition, ATO solution has completely independent NAND flash design capabilities. The NAND wafers used in SPI NAND flash are all SLC specifications, with an erase and write cycle of 100,000 times and a storage time of more than 10 years. The hardware ECC check helps customers better manage flash. This content was originally created by EEWORLD forum user dctmonica. If you need to reprint or use it for commercial purposes, you must obtain the author's consent and indicate the source
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