AMD K8L data exposed to add independent core power management

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AMD K8L data exposed to add independent core power management [Copy link]

Recently at the In-Stat Microprocessor Spring Forum, AMD senior engineer Chuck Moore revealed more information about the K8L microarchitecture, which is AMD's future quad-core architecture. As a Taiwanese motherboard manufacturer revealed earlier, its main improvement is the shared L3 Cache architecture and the use of the new generation Hyper-Transort transmission protocol, which will increase the speed to 5.2GB/s. AMD will also improve the floating point computing capability and the often criticized SSE instruction execution efficiency in the new generation K8L microarchitecture.

Chuck Moore also revealed that in order to further improve the power saving effect of the K8L architecture, each core will adopt independent power management. When some cores are idle, the voltage and clock of the idle core can be reduced without affecting other cores that are operating at full speed. The AMD K8L microprocessor architecture supports co-processors, such as those responsible for physical calculations or floating-point calculations1. It can also increase computing performance through co-processors. According to Chuck Moore, the co-processor is most likely to be released as an HTX plug-in card.
However, according to our inquiry to Taiwan's first-tier motherboard manufacturers, AMD plans to launch a four-core server processor Deerhound in the second half of 2007. It will not adopt a new architecture. Products using K8L will not appear until the first half of 2008, including the desktop processor Greyhound, the workstation processor Cadiz and the server processor Zamora.