Synchronous fifo read and write enable problem

平漂流

Synchronous fifo read and write enable problem [Copy link]

As shown in the picture, my write fifo is written one by one intermittently, and the write enable high level is a global_clk. Can the FIFO_clk be inverted? (The picture was downloaded from the Internet, and I will use the picture to speak for myself)

coyoo

According to your diagram, it is possible, but how can you ensure that your write enable always strictly follows this timing? So it is recommended to invert the write enable and write data in the inverted clock domain.

平漂流

coyoo posted on 2018-8-8 11:10 According to your diagram, it is possible, but how can your write enable ensure that it always strictly follows this timing? So it is recommended to invert the write enable and write data...

Use D flip-flop for synchronization?

平漂流

coyoo posted on 2018-8-8 11:10 According to your diagram, it is possible, but how can your write enable ensure that it always strictly follows this timing? So it is recommended to invert the write enable and write data...

When a data comes, I will generate a high level of the global-clk cycle, and then when this data is written to the fifo, a write enable of a clock cycle is generated based on this high level.

平漂流

The problem has been solved. The problem is not here. There is a small problem with the input and output signals I defined. After solving it, I found that whether FIFO_clk is inverted relative to global_clk has no effect on the final result.