FIFO read and write problems

陈士双

FIFO read and write problems [Copy link]

Hey guys, I have a question for you: When a continuous data stream is stored in an asynchronous FIFO, the read and write clocks have the same frequency but different sources, so there will be a phase difference accumulation. Will the read empty or write full situation occur over time? How can I avoid this problem?

lelee007

What is the concept of phase difference accumulation? For clocks with the same frequency, the phase difference should always be fixed, so why does it accumulate?

Isn't FIFO used to solve the problem of crossing clock domains?

lihuahua

The clock frequencies used at both ends of the asynchronous fifo read and write are different

不谏

The reading speed is faster than the writing speed.