MSP430F5529 Unified Clock System UCS

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MSP430F5529 Unified Clock System UCS [Copy link]

Experiment 2: Configure MCLK and SMCLK to XT1 (XT1 of F5529 is 32.768KHZ) /*1. Configure IO ports 5.4 and 5.5 to XT1 function. */ /*2. Configure XCAP to XCAP_3, that is, a 12PF capacitor. */ /*3. Clear the XT1OFF flag. */ /*4. Wait for XT1 to start oscillating. */ #include  

void main(void){ P1SEL |= BIT0;P1DIR |= BIT0;//Measure ACLK with P2SEL |= BIT2;P2DIR |= BIT2;//Measure SMCLK with P7SEL |= BIT7;P7DIR |= BIT7;//Measure MCLK with P5SEL |= BIT4|BIT5; //Configure to XT1 function, the crystal oscillator on the circuit board is connected to these two pins UCSCTL6 |= XCAP_3; //Configure the capacitor to be 12pF UCSCTL6 &= ~XT1OFF; //Enable XT1 /*The following is a very important step:*/ /* There may be an error when XT1 just starts oscillating, causing the clock error flag to be set, which must be cleared first*/ /*OFIFG is the Osc Fault Flag, located in SFRIFG1*/ while(SFRIFG1 & OFIFG) { //If there is a clock error UCSCTL7 &=~(XT2OFFG+DCOFFG+XT1LFOFFG); //Clear 3 clock error flags SFRIFG1&=~(OFIFG);} //Clear clock error flag UCSCTL4&=(UCSCTL4&(~(SELS_7|SELM_7)))|SELS_0|SELM_0; //Configure SMCLK and MCLK clock sources to XT1 } Experiment 3: DCO-FLL numerically controlled oscillator combined with phase-locked loop The DCO module is very important in the MSP430F5529 series chips, because starting from MSP430F4XX, MSP430 referenced the FLL module, FLL is a phase-locked loop, which can increase the system clock frequency by multiplying the frequency, thereby increasing the system speed. The DCO module needs a reference clock REFCLK to run. REFCLK can come from REFOCLK, XT1CLK and XT2CLK. It is selected by SELREF in UCSCTL3. The default XT1CLK is used, but if XT1CLK is not available, REFOCLK is used. The DCO module has two output clock signals, DCOCLK and DCOCLKDIV. The frequency multiplication formula is as follows: DCOCLK = D*(N+1)*(REFCLK/n) DCOCLKDIV = (N+1)*(REFCLK/n) Where: n is the REFCLK input clock frequency division, which can be set by FLLCLKDIV in UCSCTL3. The default is 1, that is, no frequency division; D can be set by FLLD in UCSCTL2. The default is 1, that is, 2 frequency division; N can be set by FLLN in UCSCTL2. The default value is 32. Therefore, if no settings are made after the system is powered on, the actual value of DCOCLK is 2097152, and the actual value of DCOCLKDIV is 1048576. In addition, to configure the chip operating frequency, you also need to configure DCORSEL and DCOx. The specific functions of DCORSEL and DCOx are as follows: DCORSEL is located in UCSCTL1, with a total of 3 bits, which divides the DCO into 8 frequency bands. DCOx is located in UCSCTL0, with a total of 5 bits, which divides the frequency band selected by DCORSEL into 32 frequency orders, each order is about 8% higher than the previous order. The register system can be adjusted automatically and is usually configured to 0. The following table gives the frequency adjustment range under the corresponding settings: /*Multiply 32.768KHZ to 25MHZ through DCO-FLL*/ #include  

#include “HAL_PMM.h” void delay() { volatile unsigned int I; for(I = 0; I != 5000; ++i){_NOP(); }}//delay function void main(void) { WDTCTL = WDTPW+WDTHOLD; P1SEL &= ~BIT1; P1DIR |= BIT1; P1SEL |= BIT0; //ACLK P1DIR |= BIT0; P2SEL |= BIT2; //SMCLK P2DIR |= BIT2; P7SEL |= BIT7; //MCLK P7DIR |= BIT7; P5SEL |= BIT4|BIT5; UCSCTL6 |= XCAP_3; UCSCTL6 &= ~XT1OFF;//Turn on XT1, otherwise XT1LFOFFG may report an error SetVCore(3); //Raise the Vcore voltage to the highest level to meet the frequency multiplication requirement. This function is located in HAL_PMM.H__bis_SR_register(SCG0);//This syntax is in a fixed format, which means setting the variable in the brackets. SCG0 is related to the system working mode. At this time, MCLK is suspended.UCSCTL0 = 0; //Clear first. When FLL is running, the system will automatically configure this register. Don't worry about itUCSCTL1 = DCORSEL_6; UCSCTL2 = FLLD_1 | 380;//FLLD=1,FLLN=380, then the frequency is 2*(380+1)*32.768=24.969MHZ__bic_SR_register(SCG0);__delay_cycles(782000);//System's own precise delay, unit us while (SFRIFG1 & OFIFG) {UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG); SFRIFG1 &= ~OFIFG; } UCSCTL4 = UCSCTL4&(~(SELS_7|SELM_7))|SELS_3|SELM_3; //Select DCO as clock source while(1){ P1OUT ^= BIT1; delay(); } }