There is one thing I missed before, so I will add it first: there is another module clock source: MODOSC, which generates MODCLK clock source signal, and generally only provides services for the flash control module and ADC12 module. This module is automatically turned off when not in use. When any module requests the use of this clock source, MODOSC can respond to the request without being enabled. The MODCLK in 430F5529 is 5MHZ. ****************************************************************** MSP430F5529 has multiple clock sources, and the clock sources of many modules can be freely selected. In addition, since the system power consumption is generally proportional to the operating frequency, sometimes by selecting a lower frequency clock source, under normal working conditions, it is possible to effectively reduce power consumption. Although the function library HAL_UCS.c/h has complete control functions, I think it is simpler to operate the registers directly for this chapter, because the functions are too short and there are too many. 3.1 Introduction to Unified Clock System (UCS) Unified Clock System, UCS. Reasonable clock configuration can balance the system and reduce power consumption. The MSPF5529 clock system includes 5 clock sources: ①LFXT1 external low-frequency oscillator source, 32.768KHZ, can be used as a reference source for FLL; ②XT2 external high-frequency oscillator source, 4MHZ; ③VLO (Internal very low) internal low-power low-frequency oscillator source, typically 10KHZ, with average accuracy; ④REFO internal low-frequency reference source, 32.768KHZ, often used as the reference frequency of the phase-locked loop FLL, with high accuracy, no power consumption when not in use, and its setting often refers to the setting of LPM mode; ⑤DCO (Internal digitally-controlled) internal digitally controlled oscillator source, generally set by FLL; (very useful, very important, will be discussed in detail later) Three clock signals are usually used, all of which come from the above 5 signal sources: ①ACLK (Auxiliary clock) auxiliary clock, whose clock source can be selected by software control from XT1, REFOC, VLO, DCO, DCOCLKDIV, XT2. DCOCLKDIV is obtained by dividing DCO by 1, 2, 4, 8, 16 or 32. Note that ACLK can also be divided by 1, 2, 4, 8, 16 or 32. ②MCLK (Master clock) master clock, its characteristics are exactly the same as ACLK. ③SMCLK (Subsystem master clock) subsystem clock, its characteristics are exactly the same as ACLK. 3.2 UCS operating instructions The default clock situation when powering on is (must be remembered clearly!!!): ACLK: XT1 (low-frequency mode is selected as XT1CLK clock oscillator, XT1CLK is selected as the clock source of ACLK 32.768KHZ) MCLK: DCOCLKDIV (1.048576MHZ, DCOCLK=2.097152MHZ) SMCLK: DCOCLKDIV (1.048576MHZ) In addition, the reference source of FLL defaults to XT1; If the pins connecting XT1 and XT2 are not set with PXSEL, then these two clock sources are invalid; REFOCLK, VLOCLK, and DCOCLK are available in the default state; After the system is stable, DCOCLK defaults to 2.097152MHZ, and FLL defaults to 2 division, then the frequencies of MCLK and SMCLK are both 1.048576MHZ. (How to calculate will be mentioned in Experiment 3) In addition, the selection of system reset and system working mode LPM will have a certain impact on UCS. There are too many restrictions here. For details, please refer to the UCS part of TI official data. LPM and system reset will be discussed in the next chapter. A brief summary of the operating instructions: (The following is basically nonsense, just understand it) ① The choice of VLO is the simplest, and there is no need to consider other situations; ② The selection of REFO needs to refer to different working modes and has multiple restrictions; ③ XT1 and XT2 have the same characteristics. When using it, not only the pins connected to it should be configured, but also the capacitors should be configured, and it should be noted whether it works in low-frequency or high-frequency mode. Moreover, there are different requirements in different working modes; ④ As a digitally controlled oscillator, the frequency of DCO can be adjusted not only by itself, but also by the FLL phase-locked loop; ⑤ FLL phase-locked loop is a flexible choice for frequency conversion. It can set the base frequency, select the frequency division number, and can be turned off directly to reduce power consumption; ⑥ The UCS system has a clock signal error protection mechanism; ⑦ For places with strict timing requirements, a high-precision clock source should be selected, and the modulation settings of the FLL and DCO parts should be done well; ⑧ Clock control diagrams in different modes (some clock sources are prohibited): (Just pay attention when you use it, check the table) 3.3 UCS register control operation There are 10 groups of 16-bit read/write registers, UCSCTL0-UCSCTL9. Word and byte operations are also supported, that is, UCSCTL0 includes UCSCTL0_H and UCSCTL0_L. Note: All bits marked "Reserved" are treated as 0 when read back if not specifically stated. UCSCTL0 DCO: DCO frequency selection. Select the DCO frequency and adjust it automatically during FLL operation (due to the change of MOD bits). The 5 control bits of DCO divide the DCO frequency selected by DCORSELx into 32 equal parts, with an interval of approximately 8%. MOD: Modulation bit counter. Select the modulation type, all MOD bits are automatically adjusted during FLL operation without user intervention. UCSCTL1 DCORSEL: DCO frequency range selection DISMOD: Modulator disable enable bit. 0-enable modulator; 1-disable modulator. UCSCTL2 FLLD: Prescaler (i.e. fDCO frequency division). 000-1 division, 001-2 division, 010-4 division, 011-8 division, 100-16 division, 101-32 division, 110 and 111 are all standby, the default is 32 division. FLLN: frequency multiplication factor. Set the frequency multiplication value N, N must be greater than 0, if FLLN=0, then N is automatically set to 1. UCSCTL3 SELREF: FLL reference clock selection. 000-XT1, 001-standby, the default is XT1, 010-REFO, 101-XT2, the rest are standby, the default is REFO. FLLREFDIV: FLL reference clock divider. 000-1 division, 001-2 division, 010-4 division, 011-8 division, 100-12 division, 101-16 division, 110 and 111 are all standby, the default is 16 division. UCSCTL4 SELA: ACLK clock source selection. 000-XT1, 001-VLO, 010-REFO, 011-DCO, 100-DCOCLKDIV, 101 -XT2 is XT2 when valid, otherwise DCOCLKDIV 110, 111 are reserved for later use. When XT2 is valid, the default is XT2CLK, otherwise it is DCOCLKDIV SELS: SMCLK clock source selection. The settings are the same as SELA SELM: MCLK clock source selection. The settings are the same as SELA UCSCTL5 DIVPA: ACLK external valid output division 000-1 division, 001-2 division, 010-4 division, 011-8 division, 100-16 division, 101-32 division, 110 and 111 are spare, the default is 32 division. DIVA: ACLK clock source division, setting is the same as DIVPA DIVS: SMCLK clock source division, setting is the same as DIVPA DIVM: MCLK clock source division, setting is the same as DIVPA UCSCTL6 XT2DRIVE: XT2 oscillator current drive capability adjustment, 00 minimum current consumption. XT2 oscillator operates at 4MHz to 8MHz … XT2BYPASS: XT2 bypass selection 0-XT2 is derived from the internal clock (using an external crystal) 1-XT2 is derived from an external pin input (bypass mode) XT2OFF: Turn off XT2 oscillator 0 - When the XT2 pin is set to the XT2 function and is not set to bypass mode, XT2 is turned on; 1 - When XT2 is not used as a clock source and is not used as a FLL reference clock, XT2 is turned off. XTS: XT1 working mode selection 0- low frequency mode (XCAP defines the capacitance between XIN and XOUT pins) 1- high frequency mode (XCAP bit is not used) XCAP: oscillator load capacitor selection SMCLKOFF: SMCLK shutdown control bit 0-SMCLK on 1-SMCLK off XT1OFF: Same as XT2OFF UCSCTL7 XT2OFFG: Set when XT2 fails, and OFFIFG will also be set, which needs to be cleared by software. XT1HFOFFG: Set when XT1 fails in high frequency working mode, and OFFIFG will also be set, which needs to be cleared by software. XT1LFOFFG: Set when XT1 fails in low frequency working mode, and OFFIFG will also be set, which needs to be cleared by software. DCOOFFG: Set when DCO fails, but when DCO=1 or 31, it will also be set, and OFFIFG will also be set, which needs to be cleared by software. UCSCTL8 Signal request enable: 0-corresponding signal request disabled 1-corresponding signal request allowed UCSCTL9 XT1, XT2 bypass mode input swing level (range) must be set 0-input range 0~DVCC 1-input range 0~DVIO 3.4 Experimental summary Experiment 1: Configure MCLK and SMCLK as REFOCLK, VLOCLK (oscilloscope measurement required) /* REFOCLK and VLOCLK are provided by the chip by default. As long as the chip works normally, these two clocks will work normally. Therefore, the clock configuration is very simple. You only need to modify UCSCTL4 and configure SELS and SELM to the corresponding options VLOCLK or REFOCLK*/ #include void main(void){ WDTCTL = WDTPW+WDTHOLD; P1SEL |= BIT0;//Declare that it has special functions and will not be used as ordinary I/O P1DIR |= BIT0;//ACLK output terminal, used to measure ACLK frequency, external frequency meter P2SEL |= BIT2;P2DIR |= BIT2;//SMCLK output terminal P7SEL |= BIT7;P7DIR |= BIT7;//MCLK output terminal//UCSCTL4 = UCSCTL4&(~(SELS_7|SELM_7))|SELS_1|SELM_1; //Configure SMCLK and MCLK as VLOCLK UCSCTL4 = UCSCTL4&(~(SELS_7|SELM_7))|SELS_2|SELM_2; //Configure SMCLK and MCLK as REFOCLK /* UCSCTL4&(~(SELS_7|SELM_7)) This statement is equivalent to clearing SELS and SELM first*/ while(1); }4 Experimental Summary Experiment 1: Configure MCLK and SMCLK to REFOCLK and VLOCLK (oscilloscope measurement is required) /* REFOCLK and VLOCLK are provided by the chip by default. As long as the chip works normally, these two clocks will work normally. Therefore, the clock configuration is very simple. You only need to modify UCSCTL4 and configure SELS and SELM to the corresponding options VLOCLK or REFOCLK*/ #include void main(void){ WDTCTL = WDTPW+WDTHOLD; P1SEL |= BIT0;//Declare that it has special functions and will not be used as ordinary I/O P1DIR |= BIT0;//ACLK output terminal, used to measure ACLK frequency, external frequency meter P2SEL |= BIT2; P2DIR |= BIT2;//SMCLK output terminal P7SEL |= BIT7; P7DIR |= BIT7;//MCLK output terminal //UCSCTL4 = UCSCTL4&(~(SELS_7|SELM_7))|SELS_1|SELM_1; //Configure SMCLK and MCLK as VLOCLK UCSCTL4 = UCSCTL4&(~(SELS_7|SELM_7))|SELS_2|SELM_2; //Configure SMCLK and MCLK as REFOCLK /* UCSCTL4&(~(SELS_7|SELM_7)) is equivalent to clearing SELS and SELM first*/ while(1); }4 Experimental Summary Experiment 1: Configure MCLK and SMCLK to REFOCLK and VLOCLK (oscilloscope measurement is required) /* REFOCLK and VLOCLK are provided by the chip by default. As long as the chip works normally, these two clocks will work normally. Therefore, the clock configuration is very simple. You only need to modify UCSCTL4 and configure SELS and SELM to the corresponding options VLOCLK or REFOCLK*/ #include void main(void){ WDTCTL = WDTPW+WDTHOLD; P1SEL |= BIT0;//Declare that it has special functions and will not be used as ordinary I/O P1DIR |= BIT0;//ACLK output terminal, used to measure ACLK frequency, external frequency meter P2SEL |= BIT2; P2DIR |= BIT2;//SMCLK output terminal P7SEL |= BIT7; P7DIR |= BIT7;//MCLK output terminal //UCSCTL4 = UCSCTL4&(~(SELS_7|SELM_7))|SELS_1|SELM_1; //Configure SMCLK and MCLK as VLOCLK UCSCTL4 = UCSCTL4&(~(SELS_7|SELM_7))|SELS_2|SELM_2; //Configure SMCLK and MCLK as REFOCLK /* UCSCTL4&(~(SELS_7|SELM_7)) is equivalent to clearing SELS and SELM first*/ while(1); }4 Experimental Summary Experiment 1: Configure MCLK and SMCLK to REFOCLK and VLOCLK (oscilloscope measurement is required) /* REFOCLK and VLOCLK are provided by the chip by default. As long as the chip works normally, these two clocks will work normally. Therefore, the clock configuration is very simple. You only need to modify UCSCTL4 and configure SELS and SELM to the corresponding options VLOCLK or REFOCLK*/ #include void main(void){ WDTCTL = WDTPW+WDTHOLD; P1SEL |= BIT0;//Declare that it has special functions and will not be used as ordinary I/O P1DIR |= BIT0;//ACLK output terminal, used to measure ACLK frequency, external frequency meter P2SEL |= BIT2; P2DIR |= BIT2;//SMCLK output terminal P7SEL |= BIT7; P7DIR |= BIT7;//MCLK output terminal //UCSCTL4 = UCSCTL4&(~(SELS_7|SELM_7))|SELS_1|SELM_1; //Configure SMCLK and MCLK as VLOCLK UCSCTL4 = UCSCTL4&(~(SELS_7|SELM_7))|SELS_2|SELM_2; //Configure SMCLK and MCLK as REFOCLK /* UCSCTL4&(~(SELS_7|SELM_7)) is equivalent to clearing SELS and SELM first*/ while(1); }4 Experimental Summary Experiment 1: Configure MCLK and SMCLK to REFOCLK and VLOCLK (oscilloscope measurement is required) /* REFOCLK and VLOCLK are provided by the chip by default. As long as the chip works normally, these two clocks will work normally. Therefore, the clock configuration is very simple. You only need to modify UCSCTL4 and configure SELS and SELM to the corresponding options VLOCLK or REFOCLK*/ #include void main(void){ WDTCTL = WDTPW+WDTHOLD; P1SEL |= BIT0;//Declare that it has special functions and will not be used as ordinary I/O P1DIR |= BIT0;//ACLK output terminal, used to measure ACLK frequency, external frequency meter P2SEL |= BIT2; P2DIR |= BIT2;//SMCLK output terminal P7SEL |= BIT7; P7DIR |= BIT7;//MCLK output terminal //UCSCTL4 = UCSCTL4&(~(SELS_7|SELM_7))|SELS_1|SELM_1; //Configure SMCLK and MCLK as VLOCLK UCSCTL4 = UCSCTL4&(~(SELS_7|SELM_7))|SELS_2|SELM_2; //Configure SMCLK and MCLK as REFOCLK /* UCSCTL4&(~(SELS_7|SELM_7)) is equivalent to clearing SELS and SELM first*/ while(1); }
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