Address alignment trap problem occurs when ARM controls FPGA IP core

LiFan123

Address alignment trap problem occurs when ARM controls FPGA IP core [Copy link]

   The control register uses the IP base address + offset method h2p_lw_ctl_addr=virtual_base + ( ( unsigned long )( ALT_LWFPGASLVS_OFST + PIO_LED_BASE + 0x00000001) & ( unsigned long)( HW_REGS_MASK ) ); PuTTY reports an error during compilation: Alignment trap: asd (249) PC=0x0000850a Instr=0x601a Address=0x76046001 FSR 0x811 How can I solve this problem?

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What do you add 0x00000001 for?

LiFan123

All are Pao Mo published on 2018-8-7 09:15 What do you add 0x00000001 for?

The offset of the logical address

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LiFan123 posted on 2018-8-7 11:15 Logical address offset

PIO_LED_BASE is the offset of the LED IO port

LiFan123

All are bubbled and posted on 2018-8-7 12:49 PIO_LED_BASE is the offset of the LED IO port

No, there are two registers in this IP, with logical addresses 0 and 1 respectively. PIO_LED_BASE can only represent the register with offset 0

cncqzxj

4 should be added here. Because the defined register is 32bit, that is, 4byte, so the address of R1 is +4, the address of R2 is +8, and so on. Remember last time I said that direct pointer access is very convenient: unsigned long * p =(unsigned long * )(virtual_base + ( ( unsigned long )( ALT_LWFPGASLVS_OFST + PIO_LED_BASE) & ( unsigned long)( HW_REGS_MASK ) ) ); Use p[0] and p[1] to read and write directly, the system will calculate it by itself.

LiFan123

cncqzxj posted on 2018-8-9 17:19 This place should add 4. Because the defined register is 32bit, that is, 4byte, so the address of R1 +4, the address of R2 +8, and so on. Remember...

Thank you very much