Memory Technology Suzhou R&D Center latest recruitment information 20180806

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Memory Technology Suzhou R&D Center latest recruitment information 20180806 [Copy link]

Memory Technology Suzhou R&D Center Latest Recruitment Information 20180806 Memory Technology is a company engaged in the development of storage and module products. Our products include memory (DRAM) modules, solid-state drives (SSDs) and secure embedded products. The company has a complete semiconductor industry chain system from chip planning, design, to packaging, SMT, and test design and development. It is the largest module manufacturer and top storage product developer in China. Suzhou R&D Center is in urgent need of chip design, verification, back-end, testing, firmware development and technical support personnel. Recommendations and self-recommendations are welcome. Please contact: maqiao@ramaxel.com, WeChat and QQ: 1042746432. Please remember to note your name and position when adding.
Job Category	Work Location	Job Name	Job Responsibilities	Job Requirements
Chip Category	Suzhou	IC Verification Engineer	Complete the functional verification of the delivered module, including pre-simulation and post-simulation; assist hardware and test colleagues to complete FPGA testing; participate in the construction of the entire chip verification environment, and participate in the verification of the entire system;	Bachelor's degree for more than 5 years, master's degree for more than 3 years; chip verification experience for more than 2 years; can use UVM to build chip modules and system-level verification platforms; experience in pcie/nvme/ddr protocols is preferred
	Suzhou	IC Backend Engineer	Independently complete PR/STA/PV work of digital backend block; independently complete full chip FloorPlan, Power, Clock&Reset and other work; cooperate to complete DFT, ECO, Power analysis and other related work	Bachelor's degree of 8 years, master's degree of more than 7 years; familiar with the entire flow from Netlist to layout output; Have relevant experience in backend design of 28nm and below process; have relevant experience in mass production of SOC chips; those with backend design experience of high-speed interfaces such as HDMI, DDR, PCIE, SATA, USB, etc. are preferred
	Suzhou	Front-end Design Engineer	PCIE, IP design, including architecture design, RTL coding, FPGA synthesis	Master's degree 3 years/bachelor's degree 5 years or more IC design experience, PCIE design experience is preferred; have IP architecture and design implementation capabilities, can skillfully use Verilog language for RTL design and integration, can perform synthesis, static timing analysis and formal verification, and can design FPGA prototypes
Software	Suzhou	Firmware Engineer	Responsible for the documentation, coding and maintenance of the SSD firmware module; participate in the SSD firmware project import and cooperate with the overall product debugging; cooperate with the system analysis of defective products of the solid-state storage product client; participate in the SSD firmware architecture design	Proficient in basic programming languages and algorithms; Proficient in software module testing specifications; Familiar with embedded software design and memory-constrained system design; Familiar with the management of data flow and control flow of solid-state storage systems; Participate in the development of 1/2 SSD-related products as a key developer At least master one of the following professional knowledge: A. Platform direction: Master the basic MCU architecture, master the transplantation and development of RTOS; Proficient in NAND FLASH principles, Booting principles, AES/DPP, etc. B. Interface direction: Proficient in a bus protocol (such as USB/SATA/SDIO/PCIE, etc.); Proficient in a storage class protocol (such as ATA/SCSI/eMMC, etc.);
	Suzhou	Senior Software Engineer (SD Interface)	1. Responsible for chip SD/SDIO verification; 2. Responsible for FW SD interface development and maintenance; 3. Responsible for TF card verification and mass production	1. Familiar with one or more CPU architectures and assembly languages such as ARM, MIPS, X86, PowerPC; 2. Proficient in C language and common data structures, with good coding standards and document writing skills; 3. Familiar with at least one peripheral interface protocol (USB, SD/SDIO, EMMC, SPI, etc.), with more than 3-5 years of driver development experience; 4. Those who are familiar with FPGA verification are preferred; 5. Those with SD/SDIO development experience are preferred 6. Those with project management experience are preferred.
	Suzhou	Senior Software Engineer (Backend NFC Direction)	1. Responsible for chip NFC driver verification; 2. Responsible for NAND Flash verification, including Retention test; 3. Responsible for chip SDK NFC driver HAL design and development	1. Familiar with one or more CPU architectures and assembly languages such as ARM, MIPS, X86, PowerPC; 2. Proficient in C language and common data structures, with good coding standards and document writing skills; 3. More than 3 years of driver development experience, familiar with DRAM, NOR Flash and other memories are preferred; 4. Candidates with FPGA verification experience are preferred;
Management	Suzhou	Director of Platform Design Department	Organize the formulation and review of various monitoring targets for the development of solid-state storage firmware platform related technologies, and organize and promote improvements; responsible for monitoring the R&D quality of the solid-state storage firmware platform,Promote continuous optimization of R&D quality management; l Responsible for the management of platform design group related engineers' positions, performance management, career development, capability development, etc.	Familiar with basic software development process, basic programming language and algorithm; familiar with software module test specifications; familiar with basic MCU architecture; proficient in data/command flow control, Cache management; familiar with NAND FLASH principle, Booting principle, AES/DPP, etc.; familiar with SOC FPGA basic verification process and development environment; familiar with the management of solid-state storage system data flow and control flow; familiar with the basic structure and working principle of SSD
	Suzhou	Director of Logic Verification Department	1. Lead team members to complete SOC system and IP function verification, including pre-simulation and post-simulation; 2. Complete the construction of SOC verification system; 3. Assist hardware and test colleagues to complete FPGA testing; 4. Complete the construction of simulation test models for pre-research IP or functions; 5. Participate in chip architecture design and preliminary research; 6. Participate in chip Bring Up testing.	Bachelor's degree of more than 10 years, master's degree of more than 8 years, major in microelectronics, circuit system; more than 5 years of experience in SOC system verification, familiar with SSD, eMMC and other storage chip architectures; more than 5 years of experience in SOC verification; proficient in AMBA bus protocol, and have relevant bus verification experience; familiar with ARM, Cache, DMA, DDR controllers, etc., with serious testing experience preferred; familiar with SSD, eMMC and other storage chip architectures preferred.
Please contact: maqiao@ramaxel.com Maggie Ma; WeChat and QQ number: 1042746432 Please remember to note your name and position when adding