How to write a testbench for a subroutine in vivado

刘123

How to write a testbench for a subroutine in vivado [Copy link]

There are too many programs in a project, but I don't need so many of them. I just want to see the timing diagram of one of the subroutines, but I don't know how to write a testbench. Do I need to write all the programs in one program? Or should I have different testbenches like in the project?

方法欧锦

It's very well said, I understand it completely after reading it

zhangmangui

Vivado comes with some

yet

I've been playing with this recently. There is a basic mode, and it can basically be used after some modifications.

1. Give the module a name (you can choose any name, usually add "_test" after the simulation module)

For example:

module myDesign_test;

/*/*/

endmodule

2. Define variable types

Define the input signal as reg type; define the output signal as wire type;

3. Instantiate the module and associate the input signal with the signal defined in 2.

For example:

myDesign myDesignuut(.rst(rst),

.clk(clk),

.data_in(data_in),

...........

.data_out(data_out) );

4. Generate clock module

Generate one or more clocks as needed. Generally, define the clock period as a constant.

For example:

Parameter CYCLE = 100;

always #(CYCLE) clk = ~clk; //define system clock

always @（clk） clk2 = ~clk2; // divide by two

-----I won't talk about the various methods of generating clocks

5. Clock control and reset signal control

It is usually placed in the initial module, and the reset signal is edited according to specific needs; and attention should be paid to the initialization of the clock signal, otherwise the normal clock signal cannot be generated (if not initialized, clk may default to x state, and ~x state is still x, that is, no clock drive will be generated).

For example:

initial

begin

clk = 0;

clk2 = 0;

.............//Clock related signal initialization

rst = 0;

#(3*CYCLE);

rst = 1;

#(CYCLE);

rst = 0;

......//Design the reset signal of the entire system according to the needs, and have a clear concept of timing

end

6. Initialize file operations

Basic file operations include reading and writing, which are written in an initial (only concerned with opening and closing the file, and no write operations are performed during the simulation).

The read operation requires a file written in ROM format, and a ROM cell:

For example:

reg[10:0] my_rom [2:0];

$readmemb("my_rom_file.txt",my_rom);

The write operation requires a file handle, and you must also pay attention to closing the file before the simulation ends.

For example:

integer fid;

fid = $fopen("resut.txt");

.........

#(1000000*CYCLE);

$fclose(fid);

7. Programming of control signals and output results

Program the control signal according to the specific example, and sample its output results, divided into multiple initial modules. It is necessary to form a strong sense of timing, and try to make the structure of each initial module relatively simple. At this time, most of the file write operations are called to save the simulation results.

For example:

.......

$fdisplay(fid,"%b",data_out);

.......

8. End the testbench program

Use $stop or $finish to end the program and start a new initial.

For example:

initial

begin

#(1000000*CYCLE);

$ stop;

end

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