Why introduce OC gate?

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Why introduce OC gate? [Copy link]

In actual use, sometimes it is necessary to connect the output ends of two or more NAND gates to the same wire, and transmit the data (state level) on these NAND gates through the same wire. Therefore, a new NAND gate circuit, the OC gate, is needed to realize "wired AND logic". OC gates are mainly used in three aspects: 1. Realize AND/NOR logic, used as level conversion, and used as a driver. Since the collector of the output tube of the OC gate circuit is suspended, an external pull-up resistor Rp is required to be connected to the power supply VCC when used. The OC gate uses a pull-up resistor to output a high level. In addition, in order to increase the driving ability of the output pin, the principle of selecting the pull-up resistor value should be large enough from the perspective of reducing power consumption and the chip's current sinking ability; it should be small enough from the perspective of ensuring sufficient driving current. 2. Line AND logic, that is, two output terminals (including more than two) are directly interconnected to realize the logic function of "AND". In practical applications such as bus transmission, the output terminals of multiple gates need to be connected in parallel, while the output terminals of general TTL gates cannot be directly connected in parallel, otherwise the output tubes of these gates will form a large short-circuit current (sinking current) due to low impedance, which will burn out the device. In hardware, it can be implemented with OC gates or tri-state gates (ST gates). When using OC gates to implement line AND, a pull-up resistor should be added to the output port at the same time. 3. Tri-state gates (ST gates) are mainly used in applications where multiple gate outputs share the data bus. In order to avoid multiple gate outputs occupying the data bus at the same time, only one of the enable signals (EN) of these gates is allowed to be at a valid level (such as a high level). Since the output of the tri-state gate is a push-pull low-impedance output and does not require a pull-up (load) resistor, the switching speed is faster than that of the OC gate. Tri-state gates are often used as output buffers. +++++++++++++++++++++++++++++++++++++ What are OC and OD? Open-Drain gate (open-collector OC or open-drain OD) Open-Drain means open-drain output, which is equivalent to open-collector output, that is, open-collector (OC) output in TTL. It is generally used for line-or and line-and, and some are used for current drive. Open-Drain refers to MOS tubes, and Open-Collector refers to bipolar tubes. There is no difference in usage. Open drain circuits have the following characteristics: a. Use the driving capability of the external circuit to reduce the internal drive of the IC. Or drive a load higher than the chip power supply voltage. b. Multiple open drain output pins can be connected to one line. Through a pull-up resistor, an "AND logic" relationship is formed without adding any devices. This is also the principle of I2C, SMBus and other buses to determine the bus occupancy status. If used as a totem output, a pull-up resistor must be connected. When connected to a capacitive load, the falling delay is the transistor in the chip, which is an active drive with a faster speed; the rising delay is a passive external resistor with a slow speed. If high speed is required, the resistance should be small and the power consumption will be large. Therefore, the selection of load resistance should take into account both power consumption and speed. c. The transmission level can be changed by changing the voltage of the pull-up power supply. For example, adding a pull-up resistor can provide TTL/CMOS level output, etc. d. If the open-drain pin is not connected to an external pull-up resistor, it can only output a low level. Generally speaking, open drain is used to connect devices of different levels and match the levels. The normal CMOS output stage is an upper and lower tube. Removing the upper tube is OPEN-DRAIN. The main purposes of this output are two: level conversion and line AND. Since the drain stage is open, the subsequent circuit must be connected to a pull-up resistor. The power supply voltage of the pull-up resistor can determine the output level. In this way, you can convert any level. The wired-and function is mainly used in situations where multiple circuits pull down the same signal. If this circuit does not want to pull down, it will output a high level. Because the tube on the OPEN-DRAIN is removed, the high level is achieved by an external pull-up resistor. (For a normal CMOS output stage, if one output is high and the other is low, it is equivalent to a power short circuit.) OPEN-DRAIN provides a flexible output method, but it also has its weaknesses, which is the delay of the rising edge. Because the rising edge charges the load through an external pull-up passive resistor, when the resistor is selected small, the delay is small, but the power consumption is large; conversely, the delay is large and the power consumption is small. Therefore, if there is a requirement for delay, it is recommended to use the falling edge output.