LCM Timing

fish001

LCM Timing [Copy link]

1 What is LCM LCM (LCD Module) is an LCD display module or liquid crystal module, which refers to a component that assembles liquid crystal display devices, connectors, peripheral circuits such as control and drive, PCB circuit boards, backlight sources, structural parts, etc. 2 Use of LCM 1. Timing LCD generally requires three timing signals: VSYNC, HSYNC and VCLK. VSYNC is a vertical synchronization signal. Before each frame (i.e., a screen) is scanned, the signal is valid once. The signal can be used to determine the field frequency of the LCD, that is, the number of times the screen is refreshed per second (in Hz). HSYNC is a horizontal synchronization signal. Before each line is scanned, the signal is valid once. The signal can be used to determine the line frequency of the LCD, that is, the number of times the screen scans a line from left to right per second (in Hz). VCLK is a pixel clock signal. The clock source of the LCD processed by s3c2440 is HCLK. The VCLK frequency can be adjusted through the CLKVAL in the register LCDCON1. Its formula is: VCLK＝HCLK÷[(CLKVAL＋1)×2] For example, if the frequency of HCLK is 100MHz, and you want to drive an LCD screen with a pixel clock signal of 6.4MHz, you can calculate the CLKVAL value through the above formula. The result is 6.8. After rounding (the value is 6), put it into the corresponding position in the register LCDCON1. Since CLKVAL is rounded, we substitute the rounded value into the above formula and recalculate VCLK to get VCLK＝7.1MHz. In theory, for an LCD screen of known size (that is, the horizontal display size HOZVAL and the vertical display size LINEVAL are known), as long as the VCLK value is determined, the horizontal frequency and field frequency should be known. But this is not enough, because in each frame clock signal, there will be some clocks that are not related to the screen display, which brings certain complexity to the determination of line frequency and field frequency. For example, in the HSYNC signal, the horizontal synchronization signal front shoulder (HFPD) and the horizontal synchronization signal back shoulder (HBPD) will appear successively, and in the VSYNC signal, the vertical synchronization signal front shoulder (VFPD) and the vertical synchronization signal back shoulder (VBPD) will appear successively. In these signal timings, there will be no valid pixel signals. In addition, when the HSYNC and VSYNC signals are valid, their levels must be maintained for a certain period of time. They are called the horizontal synchronization signal pulse width HSPW and the vertical synchronization signal pulse width VSPW respectively. There must be no pixel signals during this period. Therefore, these signals must be included when calculating the line frequency and field frequency. The unit of HBPD, HFPD and HSPW is the time of one VCLK, while the unit of VSPW, VFPD and VBPD is the time used to scan a line. In s3c2440, all these signals (VSPW, VFPD, VBPD, LINEVAL, HBPD, HFPD, HSPW and HOZVAL) are the result of actual value minus 1. These values are configured through registers LCDCON2, LCDCON3 and LCDCON4. Just configure these values to be consistent with the data of the relevant content in the LCD to be driven. For example, the size of the LCD screen we want to display is 320×240, so HOZVAL＝320－1, LINEVAL＝240－1. The pulse width, front shoulder and back shoulder of the horizontal synchronization signal are 30, 20 and 38 respectively, then HSPW＝30－1, HFPD＝20－1, HBPD＝38－1; the pulse width, front shoulder and back shoulder of the vertical synchronization signal are 3, 12 and 15 respectively, then VSPW＝3－1, VFPD＝12－1, VBPD＝15－1. Let's calculate the line frequency (HSF) and field frequency (VSF) in detail: HSF＝VCLK÷[(HSPW＋1)＋(HSPD＋1)＋(HFPD＋1)＋(HOZVAL＋1)] ＝7.1÷408＝17.5kHz VSF＝HSF÷[(VSPW＋1)＋(VBPD＋1)＋(VFPD＋1)＋(LINEVAL＋1)] ＝17.5÷270＝64.8Hz In some cases, the default polarity of the LCD clock signal of s3c2440 is opposite to the polarity of the controlled LCD clock signal. At this time, the polarity of some clock signals can be changed through the relevant bits of register LCDCON5.