Summary of debugging points of ADXL345 using SPI mode and VC5509A interface

Jacktang

Summary of debugging points of ADXL345 using SPI mode and VC5509A interface [Copy link]

1) Configure the McBSP0 of VC5509A in clock stop mode. At this time, CLKX is used as the SCK signal, FSX is used as the SS signal, CLKR is internally connected to CLKX, and FSR is internally connected to FSX. Here, McBSP works in master mode, DX serves as the MOSI signal; DR serves as the MISO signal. 2) The key to program writing is to correctly configure McBSP0 in clock stop mode. Using CSL to complete this configuration work is easy to implement and avoids some unnecessary errors. In the McBSP data sheet, there are detailed steps (6-8) for configuring McBSP to work in SPI mode. The following are the configuration steps: (1) Reset the transmitter and receiver. XRST=0, RRST=0. (2) Reset the sampling rate generator. GRST=0. (3) Modify the registers that affect SPI operation. Some information that needs to be modified is listed as follows: 1> According to the SPI timing diagram in the ADXL345 manual, it is concluded that data is sent on the falling edge of the SCK clock and received on the rising edge. So configure CLKSTP=10b, CLKXP=1b, CLKRP=0b. 2> CLKX acts as the SCK signal, which is generated by VC5509A. CLKX should be configured as output. So configure CLKXM=1b. 3> The clock signal is provided by the sampling rate generator of McBSP. So configure SCLKME=0b, CLKSM=1b. 4> The system clock operates at 144MHz. If the data output rate of ADXL345 is to reach 3200Hz, the SCK clock frequency needs to be higher than 2MHz. To avoid negative effects caused by too high a clock, it is recommended that the SCK clock be no higher than 5MHz. Here, the SCK frequency is set to 4MHz. So configure CLKGDV=36 (144/4=36). 5> FSX acts as the SS signal, which is an output signal; and the CS signal of ADXL345 is active at low level. So configure FSXM=1b, FSGM=0b, FSXP=1b. 6> To ensure the correctness of the FSX signal, you need to configure XDATDLY=01b and RDATDLY=01b. 7> In SPI mode, please note that only single frame mode can be used, and the frame length is fixed to 1. You need to configure XPHASE=0, RPHASE=0, XFRLEN1=0, 8> Because in clock stop mode, the sending and receiving circuits are synchronized with the same clock signal, you need to set XWDLEN1 and RWDLEN1 to the same value. Here, according to the read and write timing of ADXL345, their lengths are set to 16. (4) Enable the sampling rate generator. GRST=1. (5) Enable the sender and receiver. XRST=1, RRST=1. (6) Enable the frame synchronization logic. FRST=1. 3) During debugging, I encountered some strange phenomena. For example, even if ADXL345 is not connected, there is a lot of stray signal output on MISO, and the high level of SS signal is only 2.About 2V. Later it was found that it was due to the interference of AIC23B0. After removing the terminal matching resistor, the signal returned to normal. 4) When debugging, the program cannot enter the interrupt, and it is not easy to observe the read and write timing. Use the method of loop reading registers to clear interrupts to construct the read and write timing. At this time, you can see the change of the interrupt signal, and the SCK signal is also set to 4MHz. According to the waveform, compare the timing diagram to find the bug. This is much more efficient than simply modifying the program code. 5) About MISO signal. This signal is output by ADXL345. According to the timing diagram, the upper 8 bits should be invalid data, but the actual observed waveform and the read data show that there is indeed data in the upper 8 bits. In order to highlight the problem, it was modified to loop read 1 register, and it was found that the upper 8 bits and the lower 8 bits were the same; it was changed to loop read 2 registers, and it was found that the upper 8 bits and the lower 8 bits were interleaved. Found a rule: when reading data, the upper 8 bits are the data read last time; the lower 8 bits are the data to be read this time. So just mask the upper 8 bits of data. 6) After the MISO signal outputs a high level for the last time, there is a very slow falling edge; analysis shows that this is because ADXL345 maintains high impedance after outputting the last data (high level), so it shows a slow falling edge. It will not affect the correctness of data transmission. 7) When performing a write operation on ADXL345, a read operation is also required. Otherwise, the read data will be disordered. 8) At the beginning of the program, the interrupt signal of ADXL345 needs to be cleared to trigger the interrupt loop. Reading a register here can also enter the interrupt, but the DATA_RDY interrupt has not yet occurred, so the interrupt loop cannot be triggered. So a loop and a flag are added to detect the flag and read the register in a loop; the flag is set to 1 when a valid interrupt occurs. When the flag is detected to be 1, it indicates that the interrupt loop has been triggered, exit the read loop, and continue the following operation. However, one thing is that this method is feasible in the test program, but it is not feasible in actual use. Because if there is a problem with the ADXL345, the program will die here, making other functions impossible to implement. In practice, a finite loop can be implemented here instead of an infinite loop. 9) Finally, the rate is set to 3200Hz, and the interrupt is observed through an oscilloscope. The interrupt occurs about 300us, corresponding to 3200Hz. The low-level time of the interrupt is basically the same, indicating that the interrupt can be entered regularly, unlike the previous messy interrupt signal. The instructions for testing the interrupt function are about 9000, which takes about 54us and supports an interrupt frequency of about 19kHz. Programming Outlook: 1) Combining McBSP0 and DMA can further improve the efficiency of data reading and writing. This method is very advantageous when a large amount of data calculations need to be performed on the read data. However, it is difficult to implement, and the XINT0, RINT0, INT0 interrupts and DMA need to be coordinated. The implementation is relatively difficult. 2) Due to the limitation of the buffer, only part of the acceleration waveform can be observed. If RTDX can be added and a host computer software can be written, the collected acceleration information can be stored in the host computer, and the complete acceleration information can be observed.