I2C SPI UART difference

fish001

I2C SPI UART difference [Copy link]

The first difference is of course the name: SPI (Serial Peripheral Interface); I2C (INTER IC BUS) UART (Universal Asynchronous Receiver Transmitter) Second, the difference is in the electrical signal lines: The SPI bus consists of three signal lines: serial clock (SCLK), serial data output (SDO), and serial data input (SDI). The SPI bus can connect multiple SPI devices to each other. The SPI device that provides the SPI serial clock is the SPI host or master device (Master), and the other devices are SPI slaves or slave devices (Slave). Full-duplex communication can be achieved between the master and slave devices. When there are multiple slave devices, a slave device selection line can be added. If a general IO port is used to simulate the SPI bus, there must be an output port (SDO), an input port (SDI), and the other port depends on the type of device to be implemented. If you want to implement a master and slave device, you need an input and output port. If you only implement a master device, you only need an output port. If you only implement a slave device, you only need an input port. The I2C bus is a bidirectional, two-wire (SCL, SDA), serial, multi-master interface standard with a bus arbitration mechanism, which is very suitable for close-range, infrequent data communication between devices. In its protocol system, the device address of the destination device is always carried when transmitting data, so device networking can be realized. If a general IO port is used to simulate the I2C bus and realize bidirectional transmission, an input and output port (SDA) is required, and an output port (SCL) is also required. (Note: I2C information is relatively little understood, and the description here may be incomplete) The UART bus is an asynchronous serial port, so it is generally much more complicated than the previous two synchronous serial ports. It is generally composed of a baud rate generator (the baud rate generated is equal to 16 times the transmission baud rate), a UART receiver, and a UART transmitter. The hardware consists of two wires, one for sending and one for receiving. Obviously, if a general IO port is used to simulate the UART bus, an input port and an output port are required. Third, it is obvious from the second point that SPI and UART can achieve full-duplex, but I2C cannot; Fourth, let's see what the experts have to say! wudanyu: I2C has fewer lines, and I think it is more powerful than UART and SPI, but it is also more technically troublesome, because I2C needs to have bidirectional IO support, and uses pull-up resistors, I think the anti-interference ability is weak, and it is generally used for communication between chips on the same board, and is rarely used for long-distance communication. SPI is simpler to implement, UART requires a fixed baud rate, which means that the interval between two bits of data must be equal, while SPI does not matter, because it is a clocked protocol. quickmouse: I2C is a little slower than SPI, and the protocol is a little more complicated than SPI, but the connection is also less than the standard SPI. posted @ 2009-02-22 23:00 Chen Guangqiang Read (13) | Comment (0) | Edit SPI Bus SPI Bus Introduction Synchronous Peripheral Interface (SPI) is a full-duplex synchronous serial bus developed by Motorola. This bus is widely used to communicate with slow peripheral devices such as EEPROM, ADC, FRAM and display drivers. SPI (Serial Peripheral Interface) is a serial synchronous communication protocol, consisting of a master device and one or more slave devices. The master device initiates a synchronous communication with the slave device to complete the data exchange. The SPI interface consists of four signals: SDI (serial data input), SDO (serial data output), SCK (serial shift clock), and CS (slave enable signal). CS determines the only slave device that communicates with the master device. If there is no CS signal, there can only be one slave device. The master device initiates communication by generating a shift clock. During communication, data is output by SDO and input by SDI. Data is output by SDO at the rising or falling edge of the clock and read in by SDI at the following falling or rising edge. In this way, after 8/16 clock changes, 8/16 bits of data are transmitted. SPI communication This bus communication is based on master-slave configuration. It has the following 4 signals: MOSI: Master Out/Slave In MISO: Master In/Slave Out SCK: Serial Clock SS: Slave Select The number of "slave select" pins on the chip determines the number of devices that can be connected to the bus. In SPI transmission, data is sent and received synchronously. The clock for data transmission is based on the clock pulse from the master processor. Motorola has not defined any universal SPI clock specifications. However, the most commonly used clock settings are based on two parameters: clock polarity (CPOL) and clock phase (CPHA). CPOL defines the active state of the SPI serial clock, while CPHA defines the clock phase relative to the SO-data bit. The settings of CPOL and CPHA determine the clock edge for data sampling. Data direction and communication speed SPI transmits serial data with the highest bit first. The baud rate can be as high as 5Mbps, and the specific speed depends on the SPI hardware. For example, Xicor's SPI serial device can transmit at a speed of 5MHz. SPI bus interface and timing The SPI bus includes 1 serial synchronous clock signal line and 2 data lines. In order to exchange data with peripherals, the SPI module can configure the polarity and phase of its output serial synchronous clock according to the working requirements of the peripherals. The clock polarity (CPOL) has no significant impact on the transmission protocol. If CPOL=0, the idle state of the serial synchronous clock is low; if CPOL=1, the idle state of the serial synchronous clock is high. The clock phase (CPHA) can be configured to select one of two different transmission protocols for data transmission. If CPHA=0, the data is sampled at the first transition edge (rising or falling) of the serial synchronous clock; if CPHA=1, the data is sampled at the second transition edge (rising or falling) of the serial synchronous clock. The clock phase and polarity of the SPI master module and the peripheral device communicating with it should be consistent. The clock phase and polarity of the SPI master module and the peripheral device communicating with it should be consistent. Personally, I understand this sentence to have two meanings: First, the configuration of the master device SPI clock and polarity should be determined by the peripheral device; second, the configuration of the two should be consistent, that is, the SDO configuration of the master device is consistent with the SDO configuration of the slave device, and the SDI configuration of the master device is consistent with the SDI configuration of the slave device. Because the master and slave devices are under the control of SCLK, they send and receive data at the same time and exchange data through two bidirectional shift registers.