Application skills/Large-capacity voice recorder based on IDE hard disk[Copy link]
Abstract : This paper introduces the design method of a large-capacity voice recorder based on IDE hard disk, focusing on the hardware and software design of the large-capacity voice recorder.
Keywords : Large-capacity voice recorder, single-chip microcomputer, IDE, D6571E, PIO
With the rapid development of my country's economic construction, the demand for voice recording in the public security, railway, civil aviation, finance and other departments is growing. Users often need large-capacity voice recorders with playback time of several months or even years, but most of the voice recorders currently available in China can only record continuously for a few hundred hours (i.e. about one month). Large-capacity voice recorders are generally based on PCs, and the equipment is large and inconvenient to use. In recent years, hard disks, as data storage media, have been increasingly valued by people for their large capacity, high degree of intelligent interface, and convenient control. By giving full play to the advantages of hard disks and separating from the system host, we can develop voice recorders with ultra-large storage capacity and reliable performance for users.
This paper proposes a solution to use a single-chip microcomputer to control the hard disk to store voice data in real time. Its biggest advantage is that it can record voice for several months or even years and achieve higher performance indicators.
Even IDE hard disk big easy voice recorder features:
(1) With the microcontroller as the core and the PIO mode for hard disk reading and writing, the system's performance-price ratio can be greatly improved, making the voice recording time up to 1,500 hours (6GB hard disk). If a larger capacity hard disk is used, the voice recording time can be longer, meeting the requirements of continuous operation for several months or even years.
(2) The DSP chip D6517E is used, and its voice compression algorithm adopts TRUESPEECH Triple Rate Coder. The voice compression rate is 9.6, 7.2 or 4.4 kbps at an 8 kHz sampling frequency, and the MOS index can reach 3.98.
(3) The use of large-scale programmable logic devices (CPLDs) to integrate the system's digital logic circuits improves the system's stability and reliability. It has good versatility and can meet the needs of a variety of occasions without changing any hardware.
(4) A remote dispatch telephone interface is reserved to realize remote monitoring, inquiry and other functions.
(5) Due to the use of 4-layer PCB circuit board design, surface mount technology and ultra-thin notebook hard disk, the large-capacity voice recorder based on IDE hard disk is as small as an ordinary telephone. It can realize high-impedance parallel recording of one phone call, and can play the recorded voice locally and remotely dispatch the recorded voice.
In this system, the DSP chip D6571E is selected, and its voice compression algorithm uses the TRUESPEECH Triple Rate Coder. Since the real-time operation of the algorithm requires an operation speed of more than 22MIPS, the DSP core and algorithm code are integrated into the D6571E chip. The typical application circuit of D6571E is shown in Figure 1.
D6571E has a 16-bit bus, but it also allows the use of an 8-bit bus in a time-sharing manner. At this time, the CPU must use the HI/LO signal to indicate whether the data sent to the bus is the high 8 bits or the low 8 bits; when D6571E actively sends data to the bus, it will send an ACK signal to notify the CPU to read the data. HSTRD and HSTWR are the control lines for reading and writing. Since the TRUE-SPEECH Triple Rate Coder algorithm samples in 30ms frames and then analyzes and compresses them, whether reading compressed data or sending compressed data, it must be completed within one frame, otherwise D6571E will automatically enter a dormant state. The process of transmitting voice data to D6571E is as follows: first send a decompression control command, then receive a return status word, which contains the number of bytes required for the current frame, and the CPU will continuously send the specified number of data. After one frame is processed, D6571E will continue to send status words, and the voice can be played back continuously in this cycle. The data processing process for voice compression using D6571E is exactly the opposite. The status word contains the number of bytes obtained by compressing the current frame, and the CPU should connect to receive the specified number of data.
The D6571E chip has an industrial standard codec interface and can be directly connected to the audio codec chip with a serial PCM interface, such as the TP3054 (μ-law) and TP3057 (A-law) of National Semiconductor. The audio codec interface chip used in this system design is TP3057. The synchronization pulse, sampling clock, data signal, etc. required for the TP3057 to work can be obtained by simply connecting to the four control lines of the D6571E.
Since D6571E has rich control commands, in the design of a large-capacity voice recorder, the author used D6571E to implement functions such as digital volume control, automatic gain control, variable-speed playback, dual audio signal generation and identification, and caller ID, saving a lot of functional chips and circuit board area, making the large-capacity voice recorder that was finally designed yesterday the size of an ordinary telephone.
1.2 IDE Hard Drive Control
Using a single-chip microcomputer to control an existing hard disk can greatly improve the system's performance-price ratio. Therefore, this system uses a single-chip microcomputer to control the hard disk for voice data storage.
The hard disk drive with IDE interface provides two data transmission modes: PIO mode and DMA mode. Since PIO mode control is relatively easy, it provides a fast transmission method for programmatically controlled input/output. This mode uses high-speed data block I/O, with sectors as units, and uses interrupt request mode to exchange batch data with the CPU. When reading and writing sectors, 16 bits are transmitted at a time through the internal high-speed PIO data register. Normally, data transmission is in sectors, and an interrupt is generated for each sector data transmission. Since the maximum rate of voice compression data in this system is only 9.6kbps, and relevant data reports that the PIO disk writing speed can reach 192kbps, it can fully meet the requirements of this system.
This system uses Hitachi DK23AA-60 laptop hard drive, which has a storage capacity of 6GB and a thickness of only 9.6mm. Its pinout and definition are shown in Figure 2.
The IDE interface is a task register structure interface, and all input and output operations are completed by reading and writing the corresponding registers. The registers and address allocations in the IDE hard disk drive are shown in Table 1. Table 2 is the status register, which reflects the status of the hard disk drive after executing the command.
The definitions of each bit in the status register are as follows:
BSY: Drive busy; DRDY: Drive ready; DWF: Drive write failure; DSC: Seek end; DRQ: Request service, the drive wants to exchange one byte of data with the CPU through the data register; CORR: When a correctable read error occurs, this position is 1, and data transmission will continue; IDX: Received the integrated signal; ERR: Command execution error.
Before sending a command to the hard disk drive, it is necessary to first check whether the hard disk drive is busy (D7=1). If the hard disk drive is busy within the specified time, a timeout error is set; otherwise, it indicates that the hard disk drive is idle and can accept commands.
If the CPU wants to write data to the hard disk, the CPU first writes the necessary parameters into the corresponding address register and waits for DRDY to be valid; then the operation code is written into the command register, and the drive sets the DRQ bit of the status register, indicating that it is ready to receive data. The CPU writes the data into the sector buffer through the data register; when the sector buffer is full, the drive clears the DRQ bit and sets BSY, and the drive writes the data in the sector buffer to the disk; when writing to the disk is completed, the BSY bit is cleared and an interrupt request signal DNTRQ is sent; after receiving the interrupt signal, the CPU reads the drive status register and removes the interrupt signal INTRQ.
If the CPU wants to read data from the hard disk, it first writes the parameters into the address register and feature register (if necessary); then writes the command code into the command register, and the command starts to execute. At this time, the drive sets BSY in the status register to 1, and sends the data in the specified sector on the hard disk to the sector buffer. When the sector buffer is ready for data, it sets DRQ, clears BSY, and sends an interrupt request signal INTRQ. After the CPU detects the interrupt, it reads the status register and tests the ERR bit. If it is equal to 1, it goes into error processing; otherwise, the DRQ bit is 1, and the CPU reads data from the sector buffer. After the data is read, the drive resets the DRQ bit, and then the drive resets the BSY bit.
1.3 Working Principle
The large-capacity voice recorder based on IDE hard disk is mainly composed of a single-chip microcomputer, D6571E, an IDE interface notebook hard disk, an A-law codec chip TP3057, a programmable logic device MAX7128S, a 160×32 LCD module, a keyboard, a clock chip, a ring detection chip TCM1520A, a telephone line interface and a power supply. The system principle block diagram is shown in Figure 3.
The single-chip microcomputer is W78E52 from WINBOND. It is the control core of the whole system, completing the initialization of IDE hard disk, LCD, etc., receiving the voice data compressed by D6571E and storing it on the hard disk, and playing back the voice data on the hard disk through D6571E. W78E52 is an 8-bit single-chip microcomputer fully compatible with 8051. It adds functions such as Watchdog Timer and internal power management, and is one of the few single-chip microcomputers that can run at a maximum of 40MHz crystal oscillator. The single-chip microcomputer W78E52 in this system runs at a 40MHz crystal oscillator to increase the running speed.
The digital logic part of the whole system uses a large-scale programmable logic device MAX7128S from ALTERA, which completes the interface logic control between the microcontroller and the IDE hard disk, D6571E, LCD display and keyboard. The program design of the programmable logic device MAX7128S uses the currently more common and popular VHDL language, and is completed by compiling and simulating with MAX+plus II and FPGA Express software.
One D6571E completes the monitoring of the status of the parallel telephone. When D6571E detects a voice signal on the parallel line, it determines that the parallel telephone has an outgoing call; when the ring detection chip TCM1520A detects a ring on the parallel line, it determines that the parallel telephone has an incoming call. When the parallel telephone stores incoming and outgoing calls, D6571E starts recording voice and transmits the compressed voice data to the microcontroller in real time. The microcontroller is responsible for storing the voice data on the hard disk and attaching relevant date and time, incoming and outgoing call flags, calling and called phone numbers, and call duration and other index content for query use. When the local machine needs to play back the voice recording or remote dispatch, the microcontroller decompresses the voice compressed data on the hard disk and converts it into voice through another D6571E.
160×32 LCD can display two lines of Chinese characters in 16×16 dot matrix, with 10 Chinese characters in each line. It is mainly used to display the system date and time, prompt information or status information for the convenience of users.
The keyboard in the system can realize the playback selection of voice records and the setting of preset values for the D6571E operation, such as the selection of voice compression rate, adjustment of volume, etc.
The remote dispatch telephone line interface can realize remote monitoring and query functions. After the system detects the ringing signal on the remote dispatch telephone line, it will simulate picking up the phone and play a voice prompt to the caller. The caller can follow the voice prompt to monitor any voice record on the hard disk, and even monitor the voice being recorded by the system.
2 System Software Design
The system package contains the main program, interrupt service program and task subroutines, etc.
The main program mainly completes the initialization of the IDE hard disk, D6571E, LCD, etc., and detects whether the task table is empty. If not, it executes the corresponding task. Figure 4 shows the flow chart of the system main program.
The interrupt service program mainly includes T0 interrupt service program, INT0 interrupt service program, INT1 interrupt service program, etc. T0 interrupt service program is mainly responsible for feeding the watchdog regularly, scanning the keyboard to read key values, etc., and writing related tasks into the task table. INT0 and INT1 interrupt service programs respond to the interrupt requests of the two D6571E chips in the system respectively, and write the voice compression task of the parallel telephone call and the playback task of the recorded voice into the task table, waiting for the main program to call and execute.
The task subroutines mainly include LCD display subroutine, D6571E voice compression subroutine, D6571E voice decompression subroutine, IDE hard disk reading and writing subroutine, ringing processing subroutine, etc.
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