About the clock system of MSP430F149

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About the clock system of MSP430F149 [Copy link]

1. Overview MSP430F149 has three clock sources: external LF (XT1 is generally 32.768K), HF (XT2 is generally 8M), internal DCO. Three clock signals can be obtained from the clock system module: MCLK, SMCLK, ACLK. By default, MCLK and SMCLK signals come from DCO, and ACLK comes from LF. According to the official PDF, the DCO module is configured as RSELX=4, DCO=3 by default, so DCO should be 1M, but the oscilloscope actually measures MCLK/SMCLK as 680K, and the test temperature is about 25 degrees Celsius. Marking: MCLK master clock, SMCLK sub-clock, ACLK active clock. The second functions of P5.4, P5.5, and P5.6 correspond to MCLK, SMCLK, and ACLK clock signals, respectively, and can be measured with an oscilloscope. During the test, it was found that the last two digits of the frequency were always jumping, and the frequency stability was very poor. When the MSP430 series microcontroller selects the crystal oscillator as the clock source, the clock cycle is the crystal oscillator cycle. One machine cycle = one clock cycle, that is, each action of 430 can complete a basic operation; One instruction cycle = 1 to 6 machine cycles, depending on the specific instruction. If you choose an 8M crystal oscillator, one machine cycle is 125ns. The 51 microcontroller selects a 12M crystal oscillator, and its machine cycle is the clock cycle/12, and one machine cycle is 1us. It can be seen that the speed of MSP430 is 8 times that of 51. 2. Overview of usage 2.1 Program architecture Generally, after the system is initialized and the watchdog is turned off, the system clock needs to be configured. The configuration steps are: 1. Turn on the crystal oscillator; 2. Wait for the crystal oscillator to start. Clear OFIFG, delay, and determine whether OFIFG is 0. If it is 0, the crystal oscillator starts normally, and exit the judgment; 3. Select MCLK/SMCLK clock source; uchar iq0; BCSCTL1&=~XT2OFF; //Turn on the XT2 oscillator do { IFG1 &= ~OFIFG; // Clear the oscillator failure flag for (iq0 = 0xFF; iq0 > 0; iq0--); // Delay, wait for XT2 to start } while ((IFG1 & OFIFG) != 0); // Determine whether XT2 starts BCSCTL2 =SELM_2+SELS; // Select MCLK and SMCLK for XT2 2.2 Detailed description For DCO, different frequencies can be obtained by configuring resistors and DCO. Resistors can be configured on-chip or off-chip (DCOR is generally on-chip), and there are 8 on-chip resistors to choose from (RSELX), and 8 on-chip resistors to choose from (DCOX). 3. Related registers 1. DCOCTL DCOx Bits 7-5 DCO frequency select. These bits select which of the eight discrete DCO frequencies of the RSELx setting is selected. 2. BCSCTL0 XT2OFF Bit 7 XT2 off. This bit turns off the XT2 oscillator 0 XT2 is on 1 2-0 Resistor Select. The internal resistor is selected in eight different steps. The value of the resistor defines the nominal frequency. The lowest nominal frequency is selected by setting RSELx=0. 3. BCSCTL0 SELMx Bits 7-6 Select MCLK. These bits select the MCLK source. 00 DCOCLK 01 DCOCLK 10 XT2 oscillator not present on-chip. 11 LFXT1CLK SELS Bit 3 Select SMCLK. This bit selects the SMCLK source. 0 DCOCLK 1 XT2CLK when XT2 oscillator present on-chip. See 2.1 of this section. 4.2 Configure DCO void main(void) { WDTCTL = WDTPW +WDTHOLD; // Stop Watchdog Timer DCOCTL = DCO0 + DCO1 + DCO2; // Max DCO BCSCTL1 = RSEL0 + RSEL1 + RSEL2; // XT2on, max RSEL BCSCTL2 |= SELS; // SMCLK = XT2 P5DIR |= 0x70; // P5.6,5,4 outputs P5SEL |= 0x70; // P5.6,5,5 options while(1) { } } The minimum DCO is 128K and the maximum is 4.58M