STM32 Entry Series-STM32 Peripheral Address Mapping

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STM32 Entry Series-STM32 Peripheral Address Mapping [Copy link]

The on-chip peripherals are divided into four buses. Different buses carry different peripherals according to the speed of the peripherals. APB1 carries low-speed peripherals, and APB2 and AHB carry high-speed peripherals. The lowest address of the corresponding bus is called the base address of the bus. The bus base address is also the address of the first peripheral mounted on the bus. The APB1 bus has the lowest address, so the on-chip peripherals start from this address, also called the peripheral base address. Bus base address From Block 2 of the memory map, we can see that it is divided into 4 blocks, each with a starting address, which is the base address. Then, when the starting address of the next block deviates from the previous address, the difference is the offset, i.e., the offset relative to the base address. As shown in the figure below.

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From the above figure, we can see that the APB1 bus base address is 0x4000 0000, and the offset relative to the peripheral base address is 0, so this bus is also the base address of peripheral Block2.

Peripheral base address

There are many peripherals connected to each bus, and these peripherals will also have their own address range. The first address of the XXX peripheral, that is, the lowest address, is the base address of the XXX peripheral, also known as the XXX boundary address. For the specific boundary addresses of the STM32F1xx peripherals, please refer to the "STM32F1xx Chinese Reference Manual" P28 page, which has a detailed introduction. The meaning of learning penguins in embedded IoT intelligent hardware and other systems is easy to understand. Here we will use GPIO peripherals to explain the peripheral base address. Other peripherals are analyzed in the same way. The GPIO peripheral base address is shown in the figure below.

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From the figure, we can see that the peripheral GPIOx is connected to the APB2 bus and is a high-speed peripheral. The base address of the APB2 bus is 0x4001 0000, so the address offset of GPIOA relative to the APB2 bus is 800.

Peripheral register address

The registers of XXX peripherals are distributed in the corresponding peripheral address range. Here we take the GPIO peripheral as an example. GPIO is the abbreviation of general input and output port, and its input and output can be controlled by software. GPIO has many registers, each with a specific function. Each register is 32 bits and occupies four bytes. These registers are arranged in sequence on the base address of the peripheral. The location of the register is described by the offset address relative to the base address of the peripheral. Here we take the GPIOC port as an example to illustrate which registers GPIO has, as shown in the figure below. Here, we will use the GPIOC_BSRR register to teach you how to read the register description in the "STM32F1xx Chinese Reference Manual". If you want to know more about the register content, you can refer to the corresponding register peripheral part of the "STM32F1xx Chinese Reference Manual". First, we need to open the reference manual and find the GPIO peripheral chapter. There will be a GPIO register in it. Just find the register we want to find, as shown in the figure below. 62)]

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Below we analyze the above picture and guide you to get the information from it.

A. The red box 4 represents the name of the register we are looking for. The x in the register GPIOx_BSRR represents the STM32GPIO port, which is in the range of AE, that is, this register is available in ports such as GPIOA and GPIOB.

B. Red box 5 indicates the offset value relative to the GPIOx address. For example, we are using the GPIOC peripheral, whose base address is 0x40011000. Then the address of this register GPIOx_BSRR = 0x40011000 + 0x10 = 0x40011010. The same principle applies to other GPIO peripherals.

C. Red boxes 6 and 7 indicate the bit table of the register. 6 indicates the register number. Since a register is 32 bits, the range is 0-31. 7 indicates the permissions of the corresponding bit, w: write-only, r: read-only, rw: readable and writable. The bit permission of this register is w, so it can only be written. If you try to read this register, it is not guaranteed that its true content can be read. Some register bit permissions are read-only, which are generally used to indicate a certain working state of the STM32 peripheral. They are automatically changed by the STM32 hardware. The working state of the peripheral is determined by reading those register bits.

D.The red box 8 is the register bit function description. This is also the most important part of the register description, which details the function of each register bit. For example, there are two register bits in this register, BRy and BSy, where the y value represents the pin number, which can be 0-15. For example, BR0 and BS0 are used to control the 0th pin of GPIOx. If x represents GPIOC, it controls the 0th pin of GPIOC, while BR1 and BS1 control the 1st pin of GPIOC. The description of the BRy pin is "0: no operation will be performed on the corresponding ODRx bit; 1: reset the corresponding ODRx bit". Here, "reset" means setting the bit to 0, and "set" means setting the bit to 1; the ODRx in the description is the register bit of another register. We only need to know that when the ODRx bit is 1, the corresponding pin x outputs a high level, and when it is 0, the corresponding pin outputs a low level. If you are interested, you can check the description of the register GPIOx_ODR to understand.

Therefore, if "1" is written to BR0, the 0th pin of GPIOx will output "low level", but if "0" is written to BR0, it will not affect the ODR0 bit, so the pin level will not change. If you want the pin to output "high level", you need to write "1" to the "BS0" bit. The register bits BSy and BRy are the opposite operations.

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