A practical complementary bipolar process technology

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A practical complementary bipolar process technology Zhang Zhengyuan Zhang Zhengfan Abstract: A practical complementary bipolar process (CB) was developed under 3 μm process conditions. High-performance NPN and PNP transistors with characteristic frequencies of 3.2 GHz and 1.6 GHz were manufactured using this process and successfully integrated into a high-speed operational amplifier chip with a slew rate of up to 2200 V/μs. Keywords: complementary bipolar process; bipolar process; semiconductor manufacturing; semiconductor device; operational amplifier . Document code: TN405. 　Document identification code: A. Article number: 1004-3365 (2000) 01-0066-03 A Practical Complementary Bipolar Technology ZHANG Zheng-yuan，ZHANG Zheng-fan （Sichuan Institute of Solid-State Circuits，Chongqing 400060） Abstract : A practical 3- μ mcompl ementary bipolar process has been developed．With this technology , high performance npn and pnp transistors with an f T of 3．2 GHz and 1.6 GHz , respectively , are fabricated , which are integrated into high speed ope rational amplifier IC's with a swing rat e of 2200 V /μ s . The process experiment is described , and the results are discussed . Key words : Bipolar process s ; Complementary bipolar process ; Semiconductor manufactu ring ; Semiconductor device ; Operationalam plifier 1 Introduction 　　Complementary bipolar process technology can integrate high-performance NPN and PNP transistors on the same chip, allowing many new analog integrated circuits to operate at high speed without sacrificing key parameters such as circuit accuracy, circuit operating range and power consumption [1] . Analog Devices used the XFCB process to manufacture high-performance NPN and PNP transistors with fT of 4 GHz and 2 GHz respectively, and developed the AD8000 series of XFCB operational amplifiers; Harris Corporation also developed high-performance NPN and PNP transistors with characteristic frequencies of 8 GHz and 4 GHz respectively using the full dielectric isolation complementary bipolar process UHF-1 based on silicon-silicon bonding technology, and its corresponding product HFA3XXX series. Based on the existing process conditions, this paper develops a single-layer polysilicon emitter complementary bipolar process with a design line width of 3 μm and a minimum spacing of 5 μm, and successfully manufactures high-performance NPN and PNP transistors with fT of 3.2 GHz and 1.6 GHz respectively, and applies them to high-speed operational amplifiers with a slew rate of 2200 V/μs. The transistor structure is shown in Figure 1.

Figure 1 Transistor structure cross section 2 Process Experiment 　　Complementary bipolar processes can generally be divided into complementary bipolar processes with full dielectric isolation, complementary bipolar processes with mixed dielectric isolation, and complementary bipolar processes with PN junction isolation [2, 3] . The complementary bipolar process with full dielectric isolation is the most complex, and it is necessary to solve the problems caused by silicon-silicon bonding and trench isolation. Relatively speaking, the simplest is the complementary bipolar process with PN junction isolation, and its difficulty lies in the compatibility issues in the production of NPN and PNP tubes, such as the selection of well junction depth and well concentration, the selection of junction depth and concentration of phosphorus-based and boron-based regions, and the selection of impurity injection and annealing conditions in the emitter region. This paper is limited to process conditions and only conducts process research around PN junction complementary bipolar process technology, avoiding the technical difficulties in dielectric isolation.

2.1 Selection of N-well junction depth and concentration 　　The function of the N-well is to insulate the collector of the PNP tube from the substrate. If the N-well junction depth is too shallow, the collector region P + buried layer of the PNP tube will pass through the N-well and connect to the P-type substrate, causing the PNP to be unable to be isolated; if the N-well concentration is too high, the boron compensation in the P + buried layer is too much, and the P + buried layer junction depth is shallow, which increases the resistance of the P + buried layer, causing the RC of the PNP tube to be larger, the output capacity to be reduced, and the performance of the transistor to be affected. After SUPREM-Ⅲ simulation, the well junction depth is selected to be greater than 5 μm and the well concentration is 10 17 cm －3 . The experimentally obtained N-well process conditions are: implantation dose 5×10 13 cm －2 ; energy is 60 keV, and the annealing conditions are 2 h oxygen + 3.5 h nitrogen at 1200 ° C. 2.2 Formation technology of N + buried layer 　　In order to prevent the N + buried layer from returning too much, As impurities with small diffusion coefficient are selected as buried layer, the injection dose is 5×10 15cm －2 , and the injection energy is 100 keV. Experiments have shown that the following two methods can eliminate the injection damage and photoresist masking problems: 　　1) In order to reduce the damage caused by high-dose As injection, a thin oxide layer (about 50 μm) is oxidized before injection as an injection buffer layer to reduce injection damage; 　　2) In order to prevent high-dose and high-energy As ions from being injected into the photoresist masking area, the photoresist is cured with a curing machine before injection to improve the masking ability of the photoresist. 2.3 Consideration of P-well junction depth and impurity concentration 　　In order to reduce the collector series resistance R C of the NPN tube , the resistivity of the epitaxial layer is selected to be 1Ω . cm, and its impurity concentration is 5×10 15 cm －3 . If the well concentration is too low, the RC of the PNP tube will increase ; if the well concentration is too high, the base concentration of the PNP tube must be increased, which will make the current gain of the PNP tube difficult to adjust. If the P well junction depth is too shallow, there will be a thin epitaxial layer between the P + buried layer and the P well, which cannot achieve the purpose of reducing RC . Therefore, the P well junction depth and impurity concentration must be optimized. After simulation, the P well concentration is selected as 1×10 17 cm －3 and the junction depth is 3m. After the experiment, it is found that the injection dose of the P well is 2×10 1 3 cm －2 and the injection energy is 60keV. 2.4 Consideration of base junction depth 　　The base junction depth is the key to manufacturing high-performance transistors. The shallower the base junction depth, the higher the characteristic frequency of the transistor, but the process is very difficult and it is easy to punch-through. Therefore, in the process design, the base junction depth of the NPN tube and the PNP tube must be optimized. The emitter region of the PNP tube in this paper is formed by B + implantation annealing. Since its range is longer and its diffusion speed is faster than As, it is selected to be 0.45μm. Figure 2 is the impurity distribution curve of the base region of the PNP tube measured by the extended resistance tester. The emitter region of the NPN tube is implanted with As + . Since its diffusion coefficient is small, it is not easy to cause punch-through phenomenon in adjusting the current gain of the NPN. However, in the complementary bipolar process, in order to make the performance of both PNP and NPN transistors relatively high, the base junction depth of the NPN tube should be deeper. In the experiment, it is selected to be about 0.3μm. 2.5 Consideration of polysilicon emitter series resistance 　　The polysilicon emitter resistance includes four parts: polysilicon resistance, interface oxide layer resistance, single crystal silicon emitter resistance and metal-polysilicon contact resistance [4] . Among them, the polysilicon resistance and single crystal silicon emitter resistance are relatively small and can be ignored. The main factors are the metal-polysilicon contact resistance and the interface oxide layer resistance. The metal-polysilicon contact resistance can be improved by alloying. The resistance of the interface oxide layer increases with the thickness of the interface oxide layer, and is affected by the breakdown of the oxide layer during annealing to adjust the β. The interface oxide layer has a blocking effect on the holes in the base region of the NPN tube, suppressing the reverse injection effect of minority carriers, which is beneficial to improving the β of the transistor, but will increase the series resistance of the emitter. 2.6 Considerations for polysilicon emitter annealing process 　　Impurities in polysilicon diffuse strongly during annealing. If not well controlled, the impurity concentration in the emitter region will decrease, the injection effect of the emitter region will decrease, and it will be difficult to adjust the β of the transistor [5] . Therefore, effective methods must be used to suppress the diffusion of polysilicon impurities. Experiments have found that oxidizing a layer of oxide on the surface of polysilicon can both prevent the diffusion of impurities during annealing and reduce injection damage.

Figure 2 As impurity concentration distribution in polysilicon during the experiment (As implantation: dose 　　　1×10 16　cm －2 , energy 100 keV; 1050 °C, 5 min) 3 Results and discussion 　　After experiments, the optimized PN junction isolation complementary bipolar process flow and some process conditions are obtained: 　　material - oxidation - photolithography 1 (N well) - phosphorus injection into the well - degumming - photolithography 2 (N + buried layer area) - solid glue - As injection - degumming - annealing to push the well - photolithography P + buried layer area - boron injection - degumming - push the well - push the well - photolithography isolation area - boron diffusion - photolithography 6 (N + penetration area) - phosphorus diffusion - oxide layer removal - oxidation - deposition of Si 3 N 4 - photolithography 7 (active area) - dry etching of Si 3 N 4 - wet etching of SiO 2 - dry etching of silicon - degumming - high pressure oxidation - removal of Si 3 N 4 and SiO 2 (active area) - photolithography 8 (PNP base area) - phosphorus injection - degumming - push junction oxidation - deposition of Si 3 N 4 - photolithography 9 (NPN tube base area) - Stripping - pushing junction NPN base - photolithography 10 (emitter region and base hole of NPN and PNP tubes) - dry etching Si 3 N 4 - wet etching SiO 2 - stripping - deposition of polysilicon - polysilicon oxidation - photolithography 11 (emitter region, collector region of NPN tube and base region of PNP tube) - solidifying - As implantation - stripping - annealing to adjust β (NPN) - photolithography 12 (emitter region, collector region of PNP and base region of NPN) - boron implantation - stripping - photolithography 13 (polysilicon) - dry etching of polysilicon - annealing to adjust β of PNP tube - removal of SiO 2 on polysilicon - sputtering SiAl - photolithography 14 - alloying - passivation - photolithography 15 - intermediate testing.

The process requires 15 times of photolithography, 6 times of implantation, and 2 times of diffusion. Using this complementary bipolar process, high-performance NPN and PNP transistors were successfully developed. The characteristic frequencies were measured by HP7855 network analyzer to be 3.2 GHz and 1.6 GHz respectively. The GP diagram and frequency characteristic curve of the transistor are shown in Figures 3 to 6. The slew rate of the high-speed operational amplifier developed using this transistor parameter reaches 2200 V/μs.

Figure 3 GP diagram of PNP tube

Figure 4 Frequency characteristic curve of PNP tube

Figure 5 GP diagram of NPN tube

Figure 6 Frequency characteristic curve of NPN tube 　　We would like to express our deep gratitude to Dr. Li Ruzhang and Comrade Chen Jing from the CAE Center for their great help in the process of transistor parameter extraction. Author profile: Zhang Zhengyuan (1964~), male, graduated from the Department of Physics of Lanzhou University in 1987 with a bachelor's degree, and received a master's degree from the Department of Microelectronics of the University of Electronic Science and Technology of China in 1997. He is currently engaged in the research of semiconductor integrated circuit process technology. Author's unit: Zhang Zhengyuan (No. 24 Electronic Research Institute of the Ministry of Information Industry, Chongqing 400060) 　　　　　Zhang Zhengfan (No. 24 Electronic Research Institute of the Ministry of Information Industry, Chongqing 400060) [References] ［1］Wu Junqi. Progress of foreign bipolar ultra-high frequency technology［J］．Microelectronics，1993：23（3）：9～16． ［2］Yamaguchi T． Process and evice characterization for a 30 GHz ft sub -micrometer double poly-Si bipolar technology using BF 2 -implanted base with rapid thermal process［J］． IEEE Trans Electron Devices，1993；40（8）：1484～1494． ［3］Inoue M． Self-aligned cＡomplementary bipolar transistors fabricated with a selective-oxidation mask［J］． IEEE Trans Electron Devices，1987；34（10）：2146～ 2150． ［4］Zhang Zhengyuan. Development of a high-speed high-voltage NPN tube［J］． Microelectronics, 1997; 27 (5): 350. [5] Wang Yangyuan. Polysilicon thin film and its application in integrated circuits [M]. Beijing: Science Press, 1988. Received date: 1999-04-20 Finalized date: 1999-06-02