FET biasing method targeting battery-powered PWM applications

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FET biasing method targeting battery-powered PWM applications [Copy link]

Core device: TPA2010

Many PWM (pulse width modulation) applications, such as Class D audio amplifiers, require symmetrical drive circuits. The CMOS pair in Figure 1 consists of complementary N-channel and P-channel FET devices with gate and source connected, providing a low impedance path to either the positive or negative supply and the ability to directly drive a logic-level N-channel FET. Direct coupling of the CMOS pair and logic circuit drivers works well in PWM systems where the control device operates at the same voltage as the logic circuit. However, increasing the supply voltage of the output FET while driving the gate from a lower voltage logic circuit results in the P-channel device remaining conductive because of the difference in supply voltage.

　　To achieve the off state, the gate of the amplifier’s P-channel FET must be connected to the positive supply rail. Complementary CMOS logic-level drivers cannot accommodate the amplifier’s higher positive supply voltage, and alternative approaches, such as using commodity FET drivers and op amp level-shifting circuits, increase cost and complexity. You can add an external high-voltage N-channel FET to drive the gate of the P-channel amplifier FET (Figure 2). However, the capacitive load creates an exponentially rising characteristic on the drive waveform, causing the P-channel FET to stay in its linear operating region longer and thus limiting the switching frequency, resulting in significant power loss in the series FET.

　　The current generation of PWM systems is capable of operating at higher switching frequencies and, as shown in Figure 3, allows you to use a DC blocking coupling capacitor, C _B , between the output of the logic-level driver and the gate of the P-channel output FET . Resistor dividers R ₁ and R ₂ apply a DC bias voltage to the gate of the output FET that is equal to the difference between the supply voltage at the output and the logic voltage at the midpoint of the supply line. For example, in a 12V Class D PWM audio amplifier driven from a 5V microcontroller, the gate of the P-channel FET is biased at 9.5V (12V-5V/2). FETs that are specified for logic-level gate drive are used as output devices because other FETs do not exhibit nominal IDS characteristics at gate drive voltages of 5V or less.

　　Battery-powered amplifiers with resistor-divider output-stage biasing introduce an additional complication. As the battery voltage drops, the bias voltage drops. However, you can use a voltage-reference IC or a Zener diode, D1, to provide a constant bias voltage regardless of supply voltage variations ₍ Figure 4). This approach consumes less power than a simple resistor divider and provides more flexibility in the choice of coupling capacitors to suppress waveform degradation. A Class D audio power amplifier based on the Texas Instruments TPA2010 PWM power-amplifier IC (Reference 1) boosts the TPA2010's 2.5-W differential output to more than 200 Wrms into an 8-Ω load (Figure 5).