The Principle and Application of the Second-Order Δ-Σ Regulator ADS1202

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The Principle and Application of the Second-Order Δ-Σ Regulator ADS1202 [Copy link]

Abstract: ADS1202 is a 1-bit 10MHz 2nd-order delta-sigma precision signal conditioner chip produced by Texas Instruments (TI). This article introduces the technical characteristics, internal structure, working principle and practical application methods of ADS1202 in detail, and also improves the technical issues that need special attention when using ADS1202 in circuit design.

Keywords: Δ-∑ precision regulator A/D conversion measurement ADS1202

1 Overview

ADS1202 is a high-precision, 80dB dynamic range delta-sigma regulator, which operates on a +5V power supply. The chip's differential inputs can be directly connected to sensors or low-level signals, and with a suitable digital filter and modulation rate, it can complete 16-bit analog-to-digital conversion (A/D) without missing codes. With a modulation rate of 10MHz and a digital filter bandwidth of 10kHz, the device can maintain an effective resolution of 12bit. ADS1202 is suitable for medium-resolution measurements, and its application areas include: motor armature current measurement, general current measurement, precision conversion measurement, industrial process control, weight measurement, printing and portable instruments, pressure sensor measurement, etc.

2 Main features and internal structure

The ADS1202 is a single-channel, 2nd-order, CMOS analog regulator with the following main features:

*With 16-bit resolution;

*With 13-bit linearity;

* With resolution/speed switching function: 20μs signal delay at 10bit effective resolution; 77μs signal delay at 12bit effective resolution;

*Using a 5V single power supply, the input range is ±250mV;

*Gain error is 2%;

* Serial interface with four different modes;

*Paired binary decoding can be achieved by phase decomposition or Manchester decoding, which is suitable for one-line interface connection. ADS1202 uses 8-pin TSSOP package, its appearance and pin arrangement are shown in Figure 1, and the function of each pin is listed in Table 1. Since ESD may cause damage to the device, appropriate precautions should be taken when using it. Table 1 Pin Function

Pin Number	Pin Name	Pin Function
1	MO	Input method
2	VIN+	Non-inverting analog input
3	VIN-	Inverting analog input
4	M1	Input method
5	GND	Power Ground
6	MDAT	Modulator data output
7	MCLK	Modulator clock input or output
8	VDD	Power supply, +5V

The internal circuit structure of ADS1202 is shown in Figure 2. It can be seen from the figure that the chip consists of a second-order Δ-∑ regulator, a 20MHz RC oscillator, an interface circuit, a 2.5 reference voltage source and a buffer. When used, the operating voltage of the chip is not allowed to exceed 6V, the digital input voltage range is: GND-0.3V~VDD+0.3V, the analog input voltage range is: GND-0.4V~VDD+0.3V, and the power consumption of the chip is 0.25W.

3 Working Principle

ADS1202 uses a switch capacitor circuit to complete the differential analog input. This switch capacitor can realize the 2nd order regulation process, which can convert the input signal into a 1-bit digital stream. The sampling clock signal (MCLK) provides the switch current network, and the modulation clock signal is used for the A/D conversion process and also serves as the output data frame clock. The clock source can be located inside or outside the chip. The difference frequency of the clock allows the solution and signal bandwidth to change. The analog input signal is continuously sampled by the regulator and compared with the internal reference voltage. The digital stream appears at the output of the converter, which accurately represents the change of the analog input voltage over time.

3.1 Analog Input

The analog input of ADS1202 is based on a differential regulator structure. This input stage can achieve low system noise, high common mode rejection ratio (90dB) and excellent power supply rejection ratio. The input impedance of the analog input is determined by the input capacitor and the clock frequency of the regulator, which is also the sampling frequency of the regulator. The basic input structure of ADS1202 is shown in Figure 3. The relationship between the input impedance and the regulator clock frequency is:

AIN（Ω）=10 12/7fMCLK(MHz) The influence of input impedance should be considered in the design, because the source impedance of the input stage is very high. Therefore, there will be some loss when the signal passes through this external source impedance. There are two restrictions on the analog input signal of ADS1202. First, the current in and out of the analog input terminal is never allowed to exceed 10mA. Second, the absolute input voltage must be kept within the specified range. If the input voltage exceeds this limit, the protection diode at the front end of the converter will be turned on. In addition, when the voltage applied to any input terminal is maintained within the specified range of -320mV~+320mV, the linearity of the device can be ensured.

3.2 Regulator

When operating in mode 3, the sampling frequency (CLK) of the regulator ranges from a few MHz to 12MHz. The MCLK frequency can be reduced according to the requirements of the clock application, but the external MCLK must be twice the regulator frequency. The modulation technology is based on a 2nd-order, charge-balanced A/D converter, and its design concept is shown in Figure 4. The analog input voltage and output voltage of the 1-bit data converter (DAC) are integrated to provide an analog voltage at X2 and X3. This analog voltage appears on their respective integrators, and the outputs of these integrations change in a positive or negative direction. When the signal value at X4 is equal to the reference voltage of the comparator, the output of the comparator changes from negative to positive or from positive to negative depending on its initial state. When the output value of the comparator changes from high to low, the response of the 1-bit DAC to the next clock pulse is determined by the charge of the analog output voltage at X6, prompting the integration to proceed in the corresponding direction. The feedback from the regulator to the front end of the integrator will force the value of the integrator output to track the average value of the input. 3.3 Digital Output

When an external clock is provided to MCLK, it is used as the system clock of the chip and can also be used as the frame clock for data output. The data at the output of the regulator is a serial stream that can be read through the MDAT pin on the falling edge of MCLK. In theory, a 0V input differential signal will produce a series of 1s and 0s, 50% of the time at high level and 50% of the time at low level. A 256mV differential input signal will produce a series of 1s and 0s, 80% of the time at high level; correspondingly, a -256mV differential input signal and the resulting series of 1s and 0s, 20% of the time at high level, the relationship between the input voltage and the output modulation signal is shown in Figure 5.

3.4 Digital Interface Circuit

The analog signal connected to the input of the delta-sigma regulator is converted using the clock signal (CLK) applied to the regulator to output data from the delta-sigma regulator. In most applications, the delta-sigma regulator is directly connected to the DSP or microcontroller to provide two standard signals. The MDAT and MCLK signals provide the easiest connection method, but two signals are sometimes not the most ideal solution if the number of connections is to be reduced.

At the precise sampling moment, the receiver, DSP or other control device must sample the output data signal from the regulator. To do this, the receiver's clock signal must be sampled to synchronize with the transmitter's clock signal. The Δ-Σ regulator clock signal, receiver, filter, and clock must be synchronized. There are three ways to achieve this synchronization: the first is to use the Δ-Σ regulator and filter to receive the clock signal from the master clock; the second is for the Δ-Σ regulator to send the clock signal together with the digital signal; the third is to use the filter to obtain the clock signal from the received waveform itself. The best solution is to use the Δ-Σ regulator ADS1202 with a flexible interface, which may provide flexible output forms on the output lines MCLK and MDAT, so it is suitable for different operating modes. The control signal pins M0 and M1 can be used to select the type of signal provided. 3.5 Flexible interface circuit

The flexible interface circuit of ADS1202 is shown in Figure 6. Control signals M0 and M1 enter the demodulator, demodulate the input code and select the required working mode. The five decoded signals from the decoder control the RC oscillator, multiplexers MUX1, MUX2, MUX3 and MUX4 respectively. When the internal RC oscillator is used, the control signal from the decoder can control the RC oscillator. At the same time, MUX1 uses the INTCLK signal as the signal source of the MUX1 output signal, which is sent to the code generator. If an external clock is used, the control signal from the decoder will disable the internal RC oscillator and determine the position of MUX1. So that EXTCLK provides the output signal of MUX1 as the input of the code generator.

MUX2 can be used to select the output clock OCLK. When designing, the output clock can be controlled by the control signal from the decoder. The two signals in this design are from the code generator, one of which is half the clock frequency (CLK/2) and the other is one quarter of the clock frequency (CLK/4). These two clocks can be used as the input clock signals of MUX2. On the OCLK signal, the clock signal is input according to CLK/2 or CLK/4. On the OCLK signal, two different output modes will be selected according to the CLK/2 and CLK/4 control signals. The code generator receives the clock signal from MUX1 and divides the generated delta-sigma modulation clock into CLK/2 and CLK/4 clocks. At the same time, the continuous data string from the delta-sigma modulator is carefully processed by the encoder to generate paired binary codes, which are then output by the encoder to MUX3.

MUX3 is used to select the source of the output bit continuous data MDAT. The control signal from the decoder controls the source of MDAT. One of the two signals entering MUX3 comes directly from the Δ-Σ regulator and the other comes from the encoder.

The control signal of the decoder can select two different output modes for the MDAT signal: one continuous bit of data of the Δ-∑ modulator, or a pair of binary codes of the same signal. The last control signal from the decoder is used to control MUX4, and MUX2 is used to select the input or output clock, MCLK signal. The control signal of the decoder controls the direction of the clock. One signal entering MUX4 from MUX2 is used as the clock signal OCLK, and the other signal leaves MUX4 and provides an input to MUX1 as the external clock EXTCLK. There are two ways of the control signal MCLK from the decoder: two different ways can be selected, one is the output of the internal clock signal, and the other is the input of the external clock signal. The decoding circuit using five control signals can set the ideal working mode through the multiplexer.

3.6 Setting the working mode

ADS1202 has four working modes to choose from. The specific choice is determined by pins M0 and M1. The selection method is shown in Table 2.

Table 2 Selection of working mode

Way	Definition	M1	M0
0	Internal clock, synchronous data output	Low	Low
1	Internal clock, synchronous data output, 1/2 clock frequency	Low	high
2	Internal clock, Manchester code output	high	Low
3	External clock, synchronous data output	high	high

4 Application Design Examples

The typical application circuit of ADS1202 working in mode 0 is shown in Figure 7. This circuit measures the armature current of the motor through the shunt resistor RSENSE. In order to get better performance, the signal must be filtered first. R2 and C2 are used to filter out the noise on the in-phase input, R3 and C3 are used to filter out the noise on the lagging input, and C4 combined with R2 and R3 can be used to filter out the common-mode input noise. In this circuit, the shunt resistor is connected to the ADS1202 via three wires.

The working power supply of the chip is taken from the driving power supply on the IGBT. In order to filter the power supply, it is recommended to connect a 0.1μF decoupling capacitor. If better filtering is required, an electrolytic capacitor of 1μ~10μF can be added. The working mode control pins M0 and M1 of ADS1202 should be connected to a low level. The two output signals MCLK and MDAT should be directly connected to the optocoupler. Because the output stage has the ability to provide and absorb the same current, connecting the optocoupler can transmit forward or reverse signals without connecting a discharge resistor in parallel to the optocoupler diode. The reason is that the input driver has the ability to keep the LED diode output discharged. The digital signal processing chip (DSP) C28X or C24X can be directly connected to the output of the two channels of the optocoupler. In this circuit, the signal reaching C28X or C24X is a standard Δ-∑ modulated signal and is directly connected to the SPICLK and SPISMO pins. The Δ-∑ converter does not require word synchronization of serial data.

Figure 7 When it is necessary to reduce components, the circuit of ADS1202 working in mode 2 is shown in Figure 8. In the figure, pin M1 is high level, while M0 is low level. Only the in-phase input signal needs to be filtered. R2 and C2 are used to filter out the noise on the in-phase input terminal. The inverting input terminal is directly connected to the GND pin. The output signal from ADS1202 is Manchester code. In this case, only one signal is transmitted, so one optocoupler channel can be used instead of two channels.

5 Issues to pay attention to when designing printed circuit boards

5.1 Working power supply

When designing a printed circuit board, usually only one power supply, VDD, is needed. If there are separate analog and digital power supplies on the circuit board, it is more appropriate to connect the ADS1202 power supply to the analog power supply. Another way to control noise is to connect a 10Ω resistor to the ADS1202 power supply. Connecting a resistor and decoupling capacitor to the power pin of the ADS1202 can achieve better filtering effect. The analog power supply used must be stable and low in noise. For the ADS1202, higher resolution and power supply rejection ratio will be very necessary. The digital power supply contains high-frequency noise, which may be coupled to the analog part of the ADS1202. This noise may come from the switching power supply, microcontroller or digital signal processing chip. Usually, the external digital filter can suppress high-frequency noise at integer multiples of MCLK. Only the noise below and above these frequencies will be mixed into the transmission band of the digital filter, thus affecting the conversion result. For example: after the power is turned on, the input of the ADS1202, VIN+, VIN- and MCLK are not present, which will cause latching. If these signals appear after power is applied, the series resistor will be used to limit the input current. Experimentation is the best way to determine the proper connection between the ADS1202 and different power supplies.

Figure 8 5.2 Grounding

The analog and digital circuits must be carefully separated during design. Each part must have its own ground line and they cannot overlap. Do not connect the ground line under the converter, but connect the two with appropriate signal lines. For multiple converters, connect the two upper ground lines as close as possible to a central area of all converters. In some cases, experimentation is necessary to find the best point to connect the two ground lines together.

5.3 Circuit Decoupling

In the circuit design of ADS1202, it is important to use decoupling components. All coupling capacitors, especially 0.1μF ceramic capacitors, must be placed as close to the decoupling pins as possible. To decouple VDD to GND, 1μF and 10μF capacitors must be connected in parallel with 0.1μF capacitors. At least one 0.1μF ceramic capacitor must be used for VDD to GND decoupling, and the same applies to the power supply added to each digital component.

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