Verilog-A analog circuit behavior model and simulation

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Verilog-A analog circuit behavior model and simulation Article Category: Communication Power Supply Published on: 2005-2-14 Monday

Zhu Zhangming, Zhang Chunpeng, Yang Yintang, Fu Yongchao 　　(Institute of Microelectronics, Xidian University, Xi'an 710071)　 　　Abstract: The characteristics and model structure of the analog hardware description language Verilog-A are analyzed. Based on the trade-off between simulation speed and simulation accuracy, the Verilog-A behavioral models of analog switches, bandgap reference voltage sources and operational amplifiers are designed and implemented. According to the characteristics of digital-to-analog converters (DACs), DAC parameter test models are designed based on Verilog-A, and the behavioral model of 8-bit DACs is also established. All behavioral models are simulated and verified in the Cadence Spectre simulator. Keywords: Verilog-A; behavior; model; simulation With the continuous development of integrated circuit technology, system-on-chip (SOC) design is becoming the development direction of integrated circuit design. SOC chips integrate a large number of IP cores, such as microprocessors, digital signal processors (DSPs), analog/digital converters (ADCs), digital/analog converters (DACs), analog filters, memory, and radio frequency (RF) units, making the chip design scale far larger than previous designs. The complexity of its on-chip communication and IP core interface has also been greatly increased, making its design difficulty and complexity unprecedented [1]. SOC system verification has become a difficult point in design. SOC system verification is to perform functional verification, static timing analysis, power consumption analysis, etc. on the SOC system implemented based on the IP core to ensure correct system functions and good product performance. The previous SOC verification method was based on the mixed-signal integrated circuit simulation method, in which the simulation of the analog IP core was implemented using the Spice simulation method. Although this simulation method has high simulation accuracy, the simulation speed cannot meet the time requirements of product development, and it also puts forward new requirements for simulation convergence. Based on the analog hardware description language Verilog-A, this paper studies the behavioral model and simulation of analog circuits, and establishes accurate behavioral models of analog IP cores such as bandgap reference voltage sources and operational amplifiers. If accurate behavioral models are established for all analog IP cores, it can not only solve the system verification of SOC, but also solve the parameter testing problem of mixed-signal integrated circuits such as ADC. 　　1 Analog Hardware Description Language Verilog-A Verilog-A is a modular hardware description language that describes the structure, behavior and characteristic parameters of analog circuit systems and analog circuit units [2-3]. It can also be used to describe traditional signal systems, such as solid mechanics, fluid mechanics, thermodynamics and other systems. Similar to the simulation compilation of Spice subcircuits, the Verilog-A behavioral model can be mapped into a netlist. The netlist model includes the model name and parameters of the behavioral model, and its ports correspond to the ports of the behavioral model. Table 1 shows the structure of the Verilog-A behavioral model. 　　In order to facilitate the optimization between the performance and physical implementation of analog circuit systems, Verilog-A provides multi-level behavioral and structural models and multiple behavioral module description methods, including finite exponential generator limexp(), integral generator idt(), differential generator ddt(), delay generator delay() and many other functions used to describe analog circuit behavioral modules. By setting and combining different functions, analog circuit modules can be defined, such as various operational amplifiers, bandgap reference power sources, analog phase-locked loops (APLLs), voltage-controlled oscillators (VCOs), MOS capacitors, switched capacitor filters, digital/analog converters (DACs) and analog/digital converters (ADCs), and then the analog circuit IP core behavioral models for SOC design can be designed. By integrating the Verilog-A behavioral model of the analog circuit IP core into mixed-signal simulation environments such as Spectre, SOC design can be quickly implemented and seamless connections between IP cores can be ensured. 　　2 Analog circuit behavioral model based on Verilog-A 　　2.1 Analog switch behavioral model In analog integrated circuit design, analog switches are the most important analog devices, which are widely used in CMOS switch capacitors, sample-and-hold circuits, and other circuits. Therefore, the analog switch behavior model is the basis for studying the behavior model of mixed-signal IP cores such as CMOS switch capacitor filters and high-speed digital/analog converters. The study of analog switch behavior models must consider three practical factors: channel resistance, control signal feedthrough, and the opening and closing of signal correlation. Compared with the previous ideal switch model, the channel resistance value of the analog switch behavior model based on Verilog-A changes continuously rather than suddenly. When using Verilog-A to implement the continuous change characteristics of the analog switch, considering the convergence of the simulation behavior, the "transition" operation can be used to achieve it, but it will significantly slow down the system simulation speed. Using the characteristics of the low-pass RC filter, the analog switch behavior model can be well implemented and the high-speed simulation of the system can be guaranteed. The Cadence Spectre simulator is the same as all analog circuit simulation tools. DC operating point analysis is the basis of transient, AC and other simulation analysis, so the DC convergence of the analog switch model must be considered. According to the characteristics of DC analysis, the analog switch model must have a clear initial value, such as the output voltage equal to the input voltage. In the Verilog-A model representation, it can be clearly seen that the initial difference between the output voltage and the input voltage is zero, that is, 　　V(out, in) < +0.0 (1) 　　2.2 Bandgap reference voltage source circuit behavior model and simulation Figure 1 is a CMOS bandgap reference voltage source circuit. The operational amplifier in the figure puts the circuit in a deep negative feedback state. Q1, Q2, and Q3 are parasitic vertical bipolar junction field effect transistors (BJTs) formed by N-well and P-substrate. When the reference circuit outputs stably 　　According to the characteristics of the bandgap reference voltage source circuit, the established Verilog-A behavioral model is as follows: 　　In the Verilog-A model, in addition to defining an output voltage of 1.2 V, a temperature coefficient of 10-ppm/K and a power supply rejection ratio of 1.1 mV/V are also included. Using the Cadence Spectre simulation tool, Figure 2 (a) shows the temperature characteristics of the behavioral model, and Figure 2 (b) shows the power supply characteristics of the behavioral model. 　　2.3 Fully Differential Operational Amplifier Behavioral Model and Simulation 　　Figure 3 is a high-speed fully differential operational amplifier circuit. To establish the behavioral model of the circuit in Figure 3, appropriate operational amplifier behavioral parameters must be selected to ensure simulation accuracy and simulation speed. Based on the operational amplifier model, the behavioral parameters selected in this article are: DC open-loop gain, phase margin (PM), unity gain frequency, input offset voltage (VOS), load capacitance (CL) and load resistance (RL). These parameters can be fully reflected in the AC small signal analysis of the operational amplifier, so the core of the operational amplifier behavioral model is the AC model. The ideal model of the fully differential operational amplifier is as follows: 　　Based on the small signal model of the op amp, in the Verilog-A behavioral model, parameters such as phase margin and DC open-loop gain are directly reflected in the "initial block", but the noise model of the op amp needs to consider more practical factors, such as the slewing rate change and clipping effect caused by the nonlinearity of the MOS transistor. According to the characteristic that the conversion rate of the differential amplifier is limited by the tail current, the op amp Verilog-A behavioral model also reflects its conversion characteristics through the first-order approximation of the tail current. Figure 4 shows the simulation waveform of the fully differential op amp Verilog-A model. 　　3 Analog Circuit System Simulation Based on Verilog-A In the analog circuit system simulation, circuit simulation and post-simulation stages, the design of system simulation stimulus program is the most critical link. The traditional Spice stimulus program is no longer competent for the design needs of SOC, but Verilog-A can solve this problem better. This paper uses Verilog-A to design a stimulus program (TestBench) for the system simulation of frequency domain characteristic parameters such as the spurious-free dynamic range (SFDR) of high-speed DAC, and quickly obtains the simulation results of SFDR. The test method of DACSFDR is to input a digital sinusoidal signal at the digital input end, perform a fast Fourier transform (FFT) on the obtained analog output signal, and the difference between the first harmonic and the second harmonic is the SFDR value. In order to test the DAC parameters, a DAC model and an ADC behavior model with the same resolution are established based on Verilog-A. The ADC model is mainly used to generate various analog signals and can also be compared with the analog output signal of the DAC. Figure 5 is the parameter test system model of the DAC. 　　Figure 6 shows the simulation waveform of an 8-bit ADC. The input signal is a sine wave with a period of 1 MHz. 　　4 Conclusion Verilog-A is a high-level analog circuit hardware description language. It can realize high-level design and system verification of SOC in combination with Verilog. Based on Verilog-A language, this paper establishes behavioral models of analog switches, bandgap reference voltage sources, and operational amplifier circuits, and uses Cadence Spectre for simulation verification. Aiming at the SOC system verification application, the high-speed DAC model and parameter test model are studied, and a fast parameter test model and method are established. All Verilog-A behavioral models are simulated and verified using Cadence Spectre. 　 　　References 　　[1] Zhang Zhen, Wei Tongli. System-on-Chip Design Based on IP Modules [J]. Electronic Devices. 2002, 25 [2]: 127-142. 　　[2] OVILanguage Reference Manual [S] . Version 1.9. 　　[3] Miller Ira, Thierry Cassagnes. Verilog-AMS Eases MixedMode Signal Simulation [C] . 2001. Boston. Nanotech 2001. Excerpted from "Electronic Devices"