51 MCU controls the USB host bottom-level driver of SL811HS

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51 MCU controls the USB host bottom-level driver of SL811HS [Copy link]

Abstract: This paper introduces the hardware design and low-level driver writing of 51 MCU controlling SL811HS to realize USB host. The low-level driver part mainly describes the realization of USB bus reset, device plug-in and pull-out action detection, device speed detection and USB transmission transaction.

Introduction

Devices based on USB interface are easy to use and cost-effective, so they are widely used in people's work and life, such as U disk, mobile hard disk, mobile optical drive, USB camera, USB mouse and keyboard, etc. At the same time, the 51 series of single-chip microcomputers have attracted a large number of domestic users with their mature technology and high cost-effectiveness, and are widely used in the fields of measurement, control and automation. Therefore, if a USB host interface is added to the 51 single-chip microcomputer system to realize the control of USB slave devices, the single-chip microcomputer system can make full use of the existing various USB slave devices and greatly expand the functions of the single-chip microcomputer system.

This design realizes the addition of USB host function to the 51 single-chip microcomputer system, and adopts the solution of connecting an ordinary 51 single-chip microcomputer to a dedicated USB interface chip. Although this solution will limit the system transmission speed and lack stability, this solution has high design flexibility and is easy to transplant, which provides broad prospects for the development of low-cost products. The 51 single-chip microcomputer used in the design is the AT89S52 chip of Atmel Company, and the expansion of USB host function is realized by connecting an external dedicated USB interface chip SL811HS. CYPRESS's USB interface chip SL811HS can work in host or slave mode, supporting USB1.1 full-speed and low-speed data transmission. When working in host mode, SL811HS can automatically detect the plug-in and unplug actions of peripherals, and can automatically integrate data into USB protocol data packets for data transmission according to the requirements of the external processor (such as a single-chip microcomputer).

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Figure 1 System hardware diagram

This article will introduce the hardware design of the SL811HS controlled by the AT89S52 microcontroller and the writing of the underlying driver, with a focus on the design of the underlying driver.

The hardware schematic diagram of the hardware design

system is shown in Figure 1. The power supply voltage of AT89S52 is 5 V, and that of SL811HS is 3.3 V. Although the power supply voltages are different, according to the signal noise tolerance parameter analysis of the chip pins, the pins between AT89S52 and SL811HS can be directly connected without level conversion or buffering.

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Table 1 Hierarchical relationship of USB host enumeration operation drivers

Software Design

The USB host driver is a combination of high-level and low-level subroutines. The process of realizing USB transmission and control is the process of the higher-level subroutines calling the lower-level subroutines. When writing the USB host driver, you can proceed layer by layer from the low level to the high level.

Taking the operation of the USB host enumerating the slave device as an example, the hierarchical relationship of the subroutines required to realize this function is shown in Table 1. This article will introduce the implementation of several lower-level subroutines, including reading and writing the internal registers of SL811HS, the implementation of transmission transactions, device plug-in detection, reset, etc. Among them, "the implementation of transmission transactions" is the key and difficulty, and it is also the focus of this article.

The microcontroller reads and writes
the internal registers of

SL811HS . The subroutines for reading and writing the internal registers of SL811HS are the lowest-level subroutines. The various operations performed by the system are mainly realized by calling these subroutines to read and write the internal registers of SL811HS. For example, by reading the status register of SL811HS to obtain the status information of SL811HS, device plug-in detection, device speed detection, etc. can be realized. By writing the control byte to the relevant control registers of SL811HS, USB bus reset and USB data transmission can be realized.

From the perspective of programming structure, the SL811HS internal

register has 256 units, each of which is a byte. The first 16 units with addresses [00H]~[0FH] are the status registers or control registers of the SL811HS (collectively referred to as special registers), and the rest are data buffer registers. Table 2 lists the names and main functional meanings of the 16 special registers.

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Table 2 Introduction to SL811HS internal special registers

Implementation of MCU reading and writing SL811HS
internal registers
According to the timing diagram of SL811HS read and write control signals, write the subroutine of MCU reading and writing SL811HS internal registers, so that each control pin gives the required signal pulse according to the specified timing. In this program, the size of the MCU instruction cycle will directly affect the holding time and timing relationship of the output signal.

Initialization
The initialization operation mainly includes SL811HS chip reset, USB bus reset, device plug and unplug detection, and device USB data transmission speed detection. Through these initialization operations, SL811HS will establish a bottom-level protocol connection relationship between the USB host and the slave, and prepare for subsequent data communication.

SL811HS chip reset
The reset of the USB interface chip SL811HS resets the state of the chip, including the reset of the internal register value of the chip. To implement this operation, there is no need to read and write the internal registers of the interface chip, just input a valid reset pulse to the reset pin of the interface chip.

USB bus reset
According to the USB protocol, USB bus reset means outputting SE0 state on the USB data line and maintaining it for more than 10ms. After receiving this reset signal, the slave device connected to the USB bus will reset itself and prepare for the next USB data transmission. By setting the 4th and 3rd bits of the CtrlReg[05H] register of the interface chip to logic "01" and maintaining it for 10ms, and then restoring them to logic "00", the interface chip can generate a USB bus reset signal.

Device plug-in detection and device speed detection
At the physical layer of the USB protocol, whether the USB slave device is connected to the USB bus is known by detecting the voltage of the bus. According to the voltage level, the speed supported by the device on the USB bus can also be known (for example, in the USB1.1 protocol, there are low speed and full speed). The USB host interface chip SL811HS reflects the voltage detection results of this physical layer to the value of the status register. By reading the values of these status registers, the current device plug-in status and device speed can be known.

In addition to the above three items, the initialization operations performed by the USB host also include the setting of frame start packet enable/disable, frame synchronization setting, frame timing initial value setting, etc., which are all realized by reading and writing special registers of the interface chip.

Implementation of transfer transactions
According to the USB1.1 protocol, a transfer transaction generally includes the transmission of three packets, namely, token packet, data packet and handshake packet. There are four USB data transmission modes, namely control transfer, isochronous transfer, interrupt transfer and bulk transfer. Among them, the control transfer mode consists of at least two transfer transactions, and the other three transfer modes each consist of one transfer transaction. It can be seen that transfer transactions are crucial in USB transmission.

A typical transfer transaction contains the transmission of three packets, and the continuous data flow of these three packets is shown in Table 3.

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Table 3 Data flow diagram of a transmission transaction

When using SL811HS to design a USB host system, the user only needs to let the microcontroller set several related special registers inside SL811HS, and then enable the transfer transaction start bit (set to logic '1'), so that the interface chip can automatically complete the sending and receiving of this packet. In the example shown in Table 3, the nth packet (marker packet) and the n+2th packet (handshake packet) are both sent from the host to the slave, and the n+1th packet (data packet) is sent from the slave to the host. The transmission direction and the transmission direction of the n+2th packet are both determined by the value of the identification field in the marker packet. The rules can refer to the USB protocol.

If the data packet of the transfer transaction is sent from the slave to the host, the transfer transaction belongs to the input type and is called an input transfer transaction. Otherwise, it is called an output transfer transaction. It can be seen that the example in Table 3 is an input transfer transaction. For an input transfer transaction, the microcontroller can determine the value of the packet field by setting the special register inside SL811HS. The main fields are: the identification field, address field and endpoint field in the marker packet, and the identification field in the data packet. In the input transmission transaction, although the data packet is not sent by the host, the reason why the single-chip microcomputer still needs to set the register related to the data packet identification field is that the host will only recognize the data packet whose identification field meets the set value in this transmission transaction. The rest, such as other fields in the tag packet and the content of the handshake packet, are automatically generated by SL811HS according to the situation.

After the host interface chip SL811HS completes an input transmission transaction, if the transmission is successful, the single-chip microcomputer can read the data sent from the slave from the data buffer register of SL811HS. Here, the first address of the data buffer is specified by the single-chip microcomputer in advance by setting the control register.

For the output transmission transaction, the single-chip microcomputer also needs to set the relevant registers to determine the identification field, address field, endpoint field and identification field of the tag packet, as well as the first address of the buffer for storing the sent data, and the data in this buffer is also written by the single-chip microcomputer. Specifically

, the operation steps that the single-chip microcomputer needs to perform to control the USB host interface chip to perform a transmission transaction are as follows:
First, if it is an output transmission transaction, the data to be sent to the slave in the data packet needs to be stored in the data buffer of SL811HS.

Secondly, make relevant preparations for transmission, that is, set the four special registers in the interface chip. The names of these four registers and their functions in the transmission transaction are listed in the first four items of Table 4.

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Table 4 SL811HS special registers directly related to transfer transactions

Third, start the transfer transaction: set the 0th bit (i.e., the transfer transaction start bit) of register EP0Control[00H] or EP1Control[08H] to logic '1' to start the transfer transaction. But before that, the other bits in this register must be set (or set at the same time as the start bit). The packet fields related to this register are listed in the last item in Table 4.

Fourth, the microcontroller reads the value of register EP0Status[03H] or EP1Status[0BH] to learn the completion status of this transaction transfer.

Finally, if the transfer is successful and the transfer transaction is of input nature, the microcontroller can read the data buffer to obtain the data sent by the slave.

Conclusion

In the bottom-level driver of the 51 single-chip microcomputer controlling the USB interface chip SL811HS, the subroutine for reading and writing the internal registers of SL811HS is the lowest level. The lower-level operations of various USB transmissions, such as bus reset, plug-in detection, speed detection, and transmission transactions, are mainly implemented by reading and writing the special registers inside SL811HS. Among them, the implementation of transmission transactions directly involves the reading and writing of 5 special registers.

Based on the bottom-level driver described in this article, related high-level programs are added to enable the 51 single-chip microcomputer system to realize the enumeration control of various USB slave devices and the data exchange of U disks, which provides a broad application prospect for the development of the 51 single-chip microcomputer system, and also has a certain reference value for the design of USB hosts on other platforms.