Selection Strategy of Signal Integrity Design Tools for High-Speed Systems

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Selection Strategy of Signal Integrity Design Tools for High-Speed Systems [Copy link]

When high-speed data is transmitted through long PCB wires, it is easy to be affected by dielectric loss and become distorted. It is difficult to solve many SI/EMI design problems faced in the GHz frequency band by relying on traditional design rules. This article introduces the method of giving hierarchical design rules and loss prediction of circuit boards through the SpecctraQuest tool, as well as the use of Hspice tools to verify device models, and perform power and ground plane analysis on the selection and layout of decoupling capacitors, and use Maxwell 2D and 3D field solvers to obtain precise geometric parameters of special wiring/component structures.

With the increasing complexity of high-speed board design in communication systems, it is no longer possible to complete the entire design simulation within an acceptable accuracy range by relying on a specific CAD tool. PCB design engineers and signal integrity (SI) design engineers need to use a variety of simulation tools . In addition to price, performance, speed and accuracy, which are always the main criteria for selecting a tool set, how to use CAD tools from multiple EDA tool software vendors to achieve design goals, SI and electromagnetic interference (EMI) design rules is also an important issue of concern to Chinese design engineers. Generally speaking, a combination of excellent design and SI/EMI analysis tools should include: layout design tools, board-level simulators, accurate field solvers, and detailed simulation engines.

The tools discussed in this article include: Allegro and SpecctraQuest, Hspice, Spicelink and HFSS: Allegro is currently a common layout design tool; SpecctraQuest is used as the main tool for board-level simulation because it has the same database as Allegro, avoiding the problem of data conversion; Hspice is a tool for more accurate analysis; Spicelink and HFSS provide 2D and 3D field solutions to analyze various interconnect geometries (through holes, connectors, etc.), especially when high-frequency analysis is required.

In order to effectively use the existing CAD tools, it is necessary to select the appropriate tools at the appropriate design stage. This article takes the high-speed communication system with a transmission rate of 2.5Gbps to 12.5Gbps between the card and the motherboard as an example to introduce how to correctly use a variety of simulation tools to solve PCB design problems with speeds reaching Gbps.

Establishing Design Rules with SpectraQuest

Allegro is a layout design tool, and SpecctraQuest is a board-level simulation tool. The advantage of the combination of the two is that they share the same huge database, use the same simulation engine and a similar graphical user interface. As Allegro and SpecctraQuest are further integrated, design engineers will be able to perform layout design and simulation at the same time during the design phase. In order for the designed cards and backplanes to transmit serial data signals at 2.5Gbps and edge rates of 100ps-200ps, it is necessary to master the SI issues in this frequency band and manage them effectively. The main SI issues that need to be understood include: skin effect, dielectric loss, coupling, and driver pre-emphasis. The SpecctraQuest tool can simulate and solve the following problems:

a. Use the SignalExplorer tool to perform pre-layout analysis and extract important nodes. As circuit boards become increasingly complex, pre-layout analysis and design rule setting are becoming increasingly important. Using the SpecctraQuest schematic extraction tool, SignalExplorer can perform pre-layout analysis based on circuit parameter changes and extract important network nodes into the circuit browser to check wiring and layout post-design. Like many other circuit-level simulation tools, one of the shortcomings of SpecctraQuest is the lack of detailed modeling capabilities. In other words, the IBIS model is the only device model that can be used. Therefore, before performing analysis in SignalExplorer, the behavioral model must be reliably evaluated.

SignalExplorer can be used to solve the following problems: evaluate the geometric dimensions of the circuit board layer, estimate the loss caused by the skin effect and the medium, give the design rules for the allowed line length of high-speed data/clock, give the line spacing for controlling coupling, give the terminal type and value, and the maximum mismatch length of all differential pairs. Experience shows that the design rules obtained from the above simulations can provide valuable guidelines for engineering layout and routing, thereby greatly shortening the design cycle and reducing design risks.

b. Losses and compensation

Skin effect and dielectric loss are often considered the main problems faced by Gigabit data transmission board design. Skin effect determines the width of the line, and dielectric loss is determined by the material that makes up the PCB. To solve these two basic problems, the board-level simulator must have the ability to handle lossy transmission lines with frequency-independent parameters, and SpecctraQuest meets this requirement. Simulation and measurement results show that dielectric loss dominates in the GHz frequency band.

In communication systems, high-speed data is transmitted over long wires and is easily affected by dielectric loss and distortion. One way to overcome this loss is to use equalizers and pre-emphasis. There are several equalization methods to choose from, and this article only discusses equalization circuits using passive components. Because most devices have built-in equalization circuits, it is difficult for IBIS-type models to compensate for them.

By separating the passive components from the device and placing them on the board, we can simulate the effects of equalization. By analyzing the modified netlist with SpectraQuest, general guidelines for equalizer application can be obtained.

When the dielectric effect is not significant, the equalizer should not work. The equalizer is used to compensate for the loss of high-frequency components on long interconnects. Pre-emphasis may cause the eye diagram of shorter interconnects to deteriorate. As the interconnect grows, the dielectric loss of FR4 board material increases. The high-frequency components of the signal (corresponding to the steep rising/falling edges) disappear, while the low-frequency components are retained. In order to use the pre-emphasis function effectively, you must first estimate the length of the interconnect in the signal transmission path and then decide whether to take compensatory measures. It is not optimal to pre-emphasize all interconnects with high transmission rates.

Table 1 compares the difference in eye window and jitter when the pre-emphasis is on/off when a 2.5Gbps signal passes through differential interconnects of different lengths.

c. Coupling in the GHz band

When the data rate is lower than Gbps, coupling has always been the main factor affecting the noise index in PCB design. Since the frequency component of the coupled signal is higher than that of the intrusion signal, its loss is greater than that of the original Gbps signal, and naturally the impact on the noise index is reduced.

Most layout design tools estimate the effects of coupling based on the coupling coefficients determined by routing geometry and materials, which derives a linear estimate that limits the parallel distance, which reduces routing density. In fact, coupling will reach saturation on long routing. Ignoring the saturation effect in the estimation process will derive routing design rules that are denser than necessary. For this reason, SpectraQuest is used to perform comprehensive simulations to determine the coupling rules in the design.

For 2.5Gbps data, the typical value of the rise time is 150ps, and the saturation length is about 300mil, which means that the actual coupling line can be longer than 300mil without increasing the coupling budget value. Table 2 shows the coupling saturation parameters and losses of a signal with a rate of 2.5Gbps, a swing of 500mv, and a rise time of 110ps. The coupling reaches saturation at about 300-400mil, because the loss causes its amplitude to be greatly attenuated on long wiring. According to this rule, design engineers can route more effectively, which is more effective than the design rules given by many layout design tools.

Designing complex wiring structures with Maxwell 2D/3D

For higher transmission rates of 10G to 12.5Gpbs, FR-4 boards will produce large losses, and other boards with better loss characteristics should be used. As shown in Figure 1, a coplanar circuit board is used to transmit 10Gbps to 12.5Gbps data on the top layer of the circuit board. The board used is RO4350. The dielectric loss of this board is very low, but it can only be wired on the top/bottom layer, so surface lines are used to transmit 10GHz signals. The signal quality using a coplanar structure is better and EMI is lower. The 3D field solver should be used to calculate the line width and spacing to ensure a 50-ohm line impedance to match the output impedance of the driving circuit. The Maxwell 3D field solver can be used.

Connector Modeling

When signals are transmitted at Gbps data rates, vias, connectors, and related wire headers can cause signal integrity issues. Accurate modeling and simulation of connector and via effects are very important for predicting signal quality.

Maxwell 3D field solver is used to extract VHDM and HSD models of connectors. After the connector model is established, it should be embedded in SpecctraQuest DML format for board-level simulation of Hspice subcircuit. Generally speaking, even if a Gbps card is successfully designed, there are still many challenges in designing a backplane with a transmission rate of 5-10Gbps. Maxwell field solver helps to create connector models for such data rates.

Detailed analysis using Hspice

a. Use Hspice to analyze the power layer

At GHz frequencies, power delivery faces new challenges, requiring the use of sophisticated modeling techniques and analysis tools to obtain true (power) plane response. Hspice is a tool that enables precise swept frequency analysis and has transistor-based IC models to simulate concurrent switching noise (SSN) of interest.

For the power layer that delivers power to high-frequency differential components, a transmission line mesh model can be used to evaluate the behavior of the power/ground plane at high frequencies. For example, to analyze a pair of 2-inch × 2.5-inch power/ground planes in a PCB, the plane spacing is 3.5 mils, the edge rate is required to be 70ps, and the bandwidth is 5GHz. The general practice is to use a target impedance budget of 272m? for each differential power/ground plane pair based on the parameter indicators of a major differential component, and the transmission line mesh model is used to determine the frequency domain response of the power?ground plane. For rates above 1Gbps, it is recommended to consider lossy and lossless conditions separately to determine the impact of adding dielectric loss to the model.

The model is used for Hspice simulation, and the resonant frequency is 1.2GHz. The simulation results show that by considering the dielectric loss problem in the power/ground plane, the resonant amplitude can be greatly reduced, which helps the frequency domain response of the power/ground plane to meet the target impedance requirements. Since most high-speed serial data uses differential transmission, the power/ground plane is dedicated to the transmission of 2.5Gbps differential signals. Ideally, differential components do not absorb transient currents due to their differential characteristics. Therefore, the target impedance can actually be higher, and by reducing unnecessary PCB layers, it is also possible to avoid designing beyond the index requirements.

b. Use Hspice to evaluate components and perform high frequency analysis

Although IBIS models are widely used for board-level simulations, analysis based on transistor driver/receiver models is still critical in the evaluation of new components. As IC manufacturers increasingly provide transistor-based models in Hspice encrypted form, Hspice is becoming the only tool for component evaluation. Such simulations should include loading/unloading packaging effects and driving transmission lines of different types and lengths for the device. To achieve this, the manufacturer needs to cooperate to provide the correct model and modify the model based on the actual component situation. Once the component is determined, the IBIS model can be created and verified based on the final Hspice model and functional specifications. At higher signal rates, such as 10-12.5Gbps, behavioral models are no longer valid, and it does not make sense to try to create IBIS models for devices operating in this frequency band.

Simulation Tool Integration Process

Based on the above research and SI design guidelines, we have successfully designed a circuit board with a transceiver rate of 12.5Gbps, which transmits 2.5Gbps data to a 40Gbps device. We have discussed in detail how to use CAD tools to solve different design problems. However, one issue that design engineers often overlook is: when facing many EDA tools in the high-speed design process, when should they choose which tool? Therefore, during the design process, simulation tools should be integrated according to the following standard process:

Develop SI model using Hspice and SpectraQuest;

Use Maxwell and SpectraQuest to develop the layering strategy, layer parameters and wiring model of the circuit board;

Use Hspice to analyze the decoupling capacitor power plane;

SpecctraQuest is used for bottom-level planning, layout indicator determination, pre-routing analysis and post-routing verification.

To perform this process efficiently, hardware design engineers and design managers must master the basics of SI and EMI.

Development Trend

At present, in the field of EDA tools, in addition to dedicated signal integrity design tools for special products , the use of integrated means to meet the urgent needs of the high-speed PCB design industry for EDA tools has become an important development trend to improve the technical level of the design industry, which is reflected in the following aspects:

The boundaries of high-speed design have expanded from communication products to consumer electronics such as mobile phones and digital imaging. EDA tool suppliers have gradually realized that the tool solutions they provide must be faster, must be able to solve more complex design problems, and must be highly integrated to solve the full range of challenges faced by the PCB design industry, thereby shortening the cycle of complex high-speed circuit board design.

With the increasing number of high-speed devices, connectors, and integrated circuit applications, there is a great demand for PCB signal integrity design tools that integrate multiple modeling languages. Mentor Graphics' ICX 3.0 is an optional solution that supports SPICE, IBIS, and VHDL-AMS PCB signal integrity tools in a single simulation environment, thus avoiding the problem of development cycle delays caused by different types of models and the use of EDA tool sets from multiple sources.

As more and more high-speed PCBs use ICs with complex packages, the noise, rebound, resonance, reflection of the power/ground layers, and coupling between the wire segments and the power/ground layers will become more serious because the PCBs and ICs contain multiple, arbitrarily shaped power/ground layers, any number of vias and signal segments. PCB design inevitably has to consider IC packaging factors. How to generate frequency domain and time domain models of PCBs and ICs for system-level simulation is also an important issue facing the industry. The full-wave analysis engine integrated in the EDA tool completes the quantification and processing of the board-level model by analyzing the characteristics of the board-level electromagnetic field.