Solving Mobile RF and Mixed Signal Integration Problems

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Solving Mobile RF and Mixed Signal Integration Problems [Copy link]

Cellular phones have traditionally used superheterodyne receivers and transmitters. However, as demand for multimode terminals that include multiple standards (GSM, cdma2000, and W-CDMA) has grown, direct conversion receiver and transmitter architectures have become increasingly popular. In the past decade, integrated circuit technology has advanced significantly, making it possible to integrate a variety of different RF, mixed-signal, and baseband processing functions on a single chip.

A typical cellular transceiver (see figure) includes the RF front end, mixed signal section and actual baseband processing. For the receiver, common architectural choices include direct conversion to DC, very low intermediate frequency (IF) and direct sampling. Direct conversion to DC is subject to DC offset and low frequency noise interference, while low IF can mitigate such interference, but image rejection is a key challenge. Direct sampling of RF has some inherent drawbacks, such as low frequency noise, overlap of broadband signals and dynamic range requirements.

Figure 1: Direct-to-dc architectures are limited by dc
offset and 1/f noise issues. Other cellular transceiver architectures
include very low IF and direct sampling.

In all of the above architectures, the key challenge is to integrate analog and digital functions. Once the signal is down-converted to DC or very low intermediate frequency, unwanted interference signals will be generated along with the useful signal, and their intensity is significantly higher than the useful signal. Digital processing of this mixed signal requires a high dynamic range A/D converter, which must have excellent noise and spurious free dynamic range performance. Taking GSM communication as an example, the interference signal at 3MHz offset from the carrier is 76dB higher than the useful signal, while the interference signal at 600KHz offset is 56dB higher than the useful signal. This determines the upper limit of the A/D converter.

In addition, at the reference sensitivity level, the useful signal at the A/D input may be only 1mV (-60dBV). In order not to degrade the noise figure performance, the quantization noise floor must be low enough, and the requirement for a 1mV signal is -80dBV. On the other hand, CDMA and W-CDMA have lower signal-to-noise ratio requirements, so the tolerable quantization noise floor range is relatively wide.

High dynamic range sigma-delta converters can be selected from different types of devices ranging from continuous time converters to discrete sampling time converters. The advantage of continuous time A/D converters is that they provide anti-aliasing filters that can be embedded as part of the converter. Discrete time converters, on the other hand, require an anti-aliasing filter to be placed in front of the converter to remove spectral images.

The order of the modulator is another design parameter that affects the dynamic range. Higher order modulators can increase the dynamic range but can lead to potential stability issues. The ratio of single-bit to multi-bit quantizers can also affect the dynamic range characteristics. Each additional bit can provide 6dB of dynamic range, but this topology requires mismatch trimming in the feedback path to achieve the desired dynamic range.

In the antenna backend, early digitization helps achieve robust design and lower cost. The wide tolerance requirements of analog components can be eliminated, and the digital blocks can be scaled down in digital process geometries, thereby reducing chip size and corresponding cost. This also helps move towards a true software radio architecture, where the A/D and digital backend blocks can automatically adapt to standards such as CDMA, W-CDMA and GSM. Some of the recent requirements of multi-mode radios must be considered when choosing an architecture, such as simultaneous operation of W-CDMA and GSM during system handover, diversity reception for increased capacity, and Bluetooth capabilities. Simultaneous operation of multiple standards will not allow reuse of functional blocks, which may increase die size and power consumption.

The high dynamic range A/D is clocked by a high-speed sampling clock, so the background noise and coupled noise of the RF front end must be carefully considered during the design and layout stages. Interference from the RF sampling clock harmonics may degrade the performance of the receiver if it is within the channel bandwidth. Once the signal is digitized, a common hardware platform can be used to extract the desired signal while blocking interfering signals. Several RF functions, such as DC offset cancellation, automatic gain control, and frequency offset correction, can be performed as part of the RF before the actual data demodulation. This eases the requirements for DSP instruction speed and makes the radio control method more flexible.

Transmitter Architecture

Transmitter architectures for multiple standards include direct up-conversion, translation loops, modulation using phase-locked loops, and polar loops. The trend is toward further digitalization to reduce the analog content in the overall transmitter chain. Key challenges include leakage current, dynamic range requirements, and cost. Phase-locked loop modulation techniques using Σ-Δ modulators promise low power consumption and a simpler architectural approach.

For systems such as CDMA and W-CDMA, separation of AM and PM components is necessary. This led to the polar ring architecture, which is gaining wider application. However, there are still difficulties in using the polar ring architecture for wideband systems, where the calibration of AM and PM components and the impact of spectral distortion are very critical. Although direct modulation methods have the advantage of being compatible with multiple standards, there are still challenges in meeting the noise floor requirements. Multimode mobile phones require several large SAW filters to attenuate the noise in the receive band.

To ease the requirements on the reconstruction filter, the signal digitization performed at the transmitter can include I (in-phase) and Q (quadrature) oversampling D/A converters. This simplifies the design of the converters somewhat, as there are no interferers in the transmitter. The dynamic range required to adequately meet the spectral mask requirements still needs to be considered in the transmitter link design.

The final stage in the transmitter chain is the power amplifier, which in some systems has a maximum transmit output power approaching 3 W. Maintaining high efficiency at this power is critical. Traditionally, power amplifiers have been designed using GaAs or InGaP.

Recent trends have been toward using CMOS power amplifiers, which has the potential to integrate them on the same chip as the rest of the transmitter and reduce system cost. However, doing so still presents some challenges in terms of efficiency, thermal characteristics, and isolation.

Authors: Avarind Loke
Senior Director, Systems Engineering
Email: Avarind.Loke@skyworks-inc.com
Bala Ramachandran
Principal Engineer
Email: Bala.Ramachandran@skyworksinc.com
Skyworks Solutions, RF Systems Division