Logic interface technology of low power MSP430 microcontroller in 3V and 5V mixed system
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Abstract: The low-power MSP430 microcontroller is interfaced with traditional LSTTL, HCMOS and CMOS technologies. The 5V tolerance feature of 3V devices is especially discussed. Two level shifters are introduced. Keywords: single chip microcomputer interface circuit microcomputer hardware MSP430 ultra-low power microprocessor is a new type of single chip microcomputer launched by TI. It has a 16-bit reduced instruction structure, contains a 12-bit fast ADC/Slope ADC, contains 60K bytes of FLASH ROM, 2K bytes of RAM, and has rich on-chip resources, including ADC, PWM, several TIME, serial port, WATCHDOG, comparator, analog signal, multiple power saving modes, and extremely low power consumption. One battery can work for 10 years. It is simple to develop, the simulator is cheap, and no expensive programmer is required.
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MSP430 has the following features: 1.8V～3.6V low voltage power supply; high-efficiency 16-bit RISC CPU can ensure fast execution of tasks, shorten working time, and most instructions can be completed in one clock cycle; 6 microsecond fast startup time can extend standby time and make startup faster, reducing battery power consumption. MSP430 product series can provide a variety of memory options, simplifying the design of MSP430 in various applications; ESD protection, strong anti-interference ability. Compared with other microcontrollers, microcontrollers with Flash can reduce power consumption to 1/5 of the original, which not only reduces the circuit board space but also reduces system costs. MSP430 has so many advantages that it can be predicted that it will be widely used in the future. However, there are still many logic devices and digital devices powered by 5V batteries in use. Therefore, in many designs, 3V (including 3.3V) logic systems and 5V logic systems coexist, and different power supply voltages are mixed in the same circuit board. With the introduction of lower voltage standards, interface problems between logic devices with different power supply voltages will exist for a long time. This article discusses the interface methods between MSP430 and logic devices in 3V and 5V systems of the most commonly used LSTTL circuits, CMOS circuits and computer HCMOS circuits in microcontrollers. Understanding these methods can avoid problems when interfacing logic devices with different voltages and ensure the reliability of data transmission in the designed circuit.
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1 Problems arising from different logic levels and interfaces In mixed voltage systems, there are three main problems when logic devices with different power supply voltages interface with each other: the first is the limitation of the maximum allowable voltage applied to the input and output pins; the second is the cross-current problem between the two power supplies; and the third is the input conversion threshold level that must be met. Devices usually have limitations on the voltage applied to the input pins or output pins. These pins are connected to Vcc by diodes or discrete components. If the input voltage is too high,  the current will flow to the power supply through the diode or discrete component. For example, if a 5V signal is connected to the input of a 3V device, the 5V power supply will charge the 3V power supply, and the continuous current will damage the diode and circuit components. When in standby or power-off mode, the 3V power supply drops to 0V, and a large current will flow to the ground, which pulls the high-level voltage on the bus down to the ground. These situations will cause data loss and component damage. It must be noted that whether in the 3V working state or the 0V state, current is not allowed to flow directly to Vcc. In addition, there are many different situations when using 5V devices to drive 3V devices, and there are also different situations for the conversion levels between various circuits. The driver must meet the input switching levels of the receiver with enough margin to avoid damage to circuit components. 2 3V logic devices with 5V tolerant inputs 3V logic devices that can have 5V input tolerance include LVC, LVT, ALVT, LCX, LVX, LPT and FCT3 series. In addition, Philips ALVC without bus hold input is also 5V tolerant. 2.1 ESD protection circuit 3V devices can have a 5V input tolerance. Generally, the input end of a digital circuit has an electrostatic discharge (ESD) protection circuit. As shown in Figure 1 (a), the traditional CMOS circuit uses grounded diodes D1 and D2 to limit the negative high voltage, and the positive high voltage is clamped by diode D3. In order to prevent current from flowing to the Vcc power supply, the maximum input voltage of this circuit is limited to Vcc+0.5V. For devices with Vcc of 3V, the input voltage allowed is too low when the input end is directly interfaced with the output end of most 5V devices. The voltage added to the input end of most 3V systems can reach more than 3.6V. Some 3V systems can use two MOS field effect tubes or transistors T1 and T2 instead of diodes D1 and D2, as shown in Figure 1 (b). The role of T1 and T2 is equivalent to fast acting diodes to limit high voltage. Since the diode D3 connected to Vcc is removed, the maximum input voltage is not limited by Vcc. Typically, the breakdown voltage of this circuit is between 7 and 10V, so it can be suitable for any 5V system input voltage. From the above analysis, it can be seen that the input end of the improved 3V system with ESD protection circuit can be interfaced with the output end of the 5V system. 2.2 Bus Protection Circuit The bus protection circuit has a MOS field effect transistor used as a pull-up or pull-down device to protect the input terminal from the last valid logic level when the input terminal is floating (high impedance). The circuit in Figure 2 (a) is a bus protection circuit of an LVC device, and improved measures are taken to make its input terminal have a 5V tolerance. The basic principle is as follows: the P-channel MOS field effect transistor has an inherent parasitic diode, which is connected between the drain and the substrate. Usually the source and the substrate are connected together, which limits the input voltage to not be higher than Vcc+0.5V. The current measure is to connect the source and the substrate with a normally closed contact S1. When the input voltage is 0.5V higher than Vcc, the comparator closes S2 and opens S1. The input current will not flow to Vcc through the diode, making the input have a 5V tolerance. Figure 2 (b) is an example of a bus holding circuit for LVT and LAVT devices. This circuit uses a series Schottky diode D to eliminate the current path from the input to Vcc, so that it can withstand a 5V input voltage. For the overall maintenance of 3V, the LVC, LVT and ALVT series devices can withstand an input voltage of 5V. However, for the 3V ALVC, VCX and other series devices, their input voltage is limited to Vcc+0.5V.
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Figure 3 is a simplified form of the output circuit for 3V CMOS devices. When the output voltage is higher than Vcc+0.5V (diode drop), the internal diode of the P-channel MOS field effect transistor will form a current path from the output to Vcc. This circuit requires a protection circuit when connected to a 5V device. Figure 4 is a CMOS device output circuit with a protection circuit. When the output voltage is higher than Vcc, the comparator opens S1, closes S2, and the current path disappears. In this way, it can be connected to a 5V device in the tri-state mode. 2.3 biCMOS output circuit The biCMOS output circuit of the LVT and ALVT devices is shown in Figure 5. It uses bipolar NPN transistors and CMOS field effect transistors to obtain an output voltage swing that meets the power supply voltage requirements. Current will not flow back to Vcc through the NPN bipolar transistor, but the internal diode in the P-channel MOS field effect transistor still forms a current path from the output to Vcc (for simplicity, the diode is not drawn in Figure 5). Therefore, this circuit cannot be connected to a voltage higher than Vcc.
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The protection circuit added to the circuit of Figure 5 is shown in Figure 6. A reverse-biased Schottky diode is added to prevent current from flowing from the output to Vcc. The output of Figure 6 shares a bus with the 5V driver. In tri-state mode, the circuit can be protected. When there is a bus contention, that is, both drivers drive the bus at a high level, the comparator disconnects the P-channel MOS field effect transistor. When the 3V device is in standby mode and the 3V power supply is 0, the comparator and Schottky diode can provide protection. 3 Parameters of interface circuit After understanding why 3V devices have 5V tolerance, before connecting MSP430 with LSTTL, HCMOS, and CMOS circuits, we must first understand the parameters of various circuits and devices, as shown in Table 1.
Table 1 Parameters of various circuits and devices Parameter
circuit | Supply voltage range | Input Level | Output Level | | V (V) | VIH (V) | VIL (V) | VOH (V) | VOL (V) | | LSTTL | 4.5～5.5 | 2 | 0.8 | 2.7 | 0.4 | | CMOS | 3～18（Vcc=5） | 3.5 | 1.5 | 4.5 | 0.5 | | HCMOS | 2～6 | 3.5 | 1 | 5.2 | 0.4 | | MSP430 | 1.83.6 | 0.8Vcc | 0.2Vcc | Vcc-0.6 | 0.6 | | ALVT Series | 3.3 or 2.5 | 1.7 | 0.8 | 2.0 | 0.2～0.55 | | LVC Series | 1.65～5.5 | 0.7Vcc | 0.3Vcc | 2.7～5.5 | 0.1～0.55 | 4 Interface Implementation The main problem when logic devices with different power supply voltages interface with each other is the coordination of logic signal levels, that is, the output level of the front-stage circuit must meet the input level requirements of the back-stage circuit. In addition, there is the coordination of load current, that is, the output current of the front-stage circuit should be greater than the input current requirements of the back-stage circuit, and at the same time, it should not cause damage to the device. In addition, in high-speed or severe interference situations, the adverse effects of the interface on the system and anti-interference performance must be considered. Here we mainly discuss the coordination of logic signal levels. Because the load current coordination problem is only a load capacity. The anti-interference problem can be ignored using the methods mentioned in this article. 4.1 LSTTL-MSP430 As shown in Table 1, the high-level output voltage VOH of the LSTTL circuit is about 2.7V, the high-level input of MSP430 is about 0.8VCC, the low-level output voltage VOL of the LSTTL circuit is about 0.4V, and the low-level input voltage VIL of MSP430 is 0.2VCC. If 0.8Vcc is less than 2.7V and 0.2Vcc is greater than 0.4V, there is no problem of matching the logic signal level, and it can be connected directly. If 0.8Vcc is greater than 2.7V or 0.2Vcc is less than 0.4V, there will be a problem of matching the logic signal level. In order to increase the output high level of the LSTTL circuit, TI's LVC series is used. From Table 1, it can be seen that the high-level output voltage and low-level output voltage of the LVC series products meet the requirements.
 screen.width-460)this.width=screen.width-460" vspace=10 border=0> 4.2 CMOS-MSP430 When interfacing, use the same power supply for CMOS and MSP430, for example, 3V power supply can be used for direct driving. If the actual situation does not allow, according to Table 1, CMOS can be used to drive MSP430 through ALVT series devices. 4.3 HCMOS-MSP430 As with the above CMOS analysis, ALVT is also used to drive MSP430. 4.4 MSP430 drives LSTTL, CMOS and HCMOS The output pins (P0.x, P1.x, P2.x, P3.x, P4.x, Oy) of the MSP430 have specified external resistors. The size of the external resistor depends on the size of the power supply voltage Vcc. If the output current is larger than the specified value, an output driver is required. Figure 7 shows the minimum value of the resistor that limits the output current of the MSP430. Designed with Vcc=3V, these devices can drive LSTTL, HCMOS and CMOS circuit interfaces that require large currents. 5 Two Level Shift Devices 5.1 Dual-supply level shifter 74LVC4245 The 74LC4245 is a dual-power level shifter, as shown in Figure 8. The 5V end uses a 5V power supply as Vcc (A), while the 3V end uses a 3V power supply as Vcc (B). Its function is similar to the commonly used transceiver 74LVC245, except that it uses two power supplies instead of one. The level shifting of the 74LVS4245 is performed internally. The dual power supply can ensure that the output swing of both ports can reach the full power supply amplitude and has good noise suppression performance. Therefore, this device is ideal for driving 5V CMOS devices. The disadvantage is that the power consumption is increased.
5.2 74LVC07 A relatively simple level shift device is the 74LVC07. It uses an open-drain buffer to drive a 5V CMOS device, as shown in Figure 9. Its output has a pull-up resistor R connected to the 5V power supply. The low-power MSP430 coexists with LSTTL, HCMOS and CMOS devices in a system for a long time. When designing such a system, it is necessary to analyze the interface problems of the logic devices and ensure the reliability of data transmission between devices with different voltages.
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