Discussion about interrupt system

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The concept of interruption

What is interruption? Let's introduce it from an example in life. You are reading a book at home, and suddenly the phone rings. You put down the book, answer the phone, talk to the caller, then put down the phone and come back to read your book. This is the phenomenon of "interruption" in life, that is, the normal working process is interrupted by external events.

A careful study of interrupts in life is also very helpful for us to learn interrupts in single-chip microcomputers. First, what can cause interrupts? Many events in life can cause interrupts: someone presses the doorbell, the phone rings, your alarm goes off, the water you boiled boils... and so on. We call the events that can cause interrupts interrupt sources. There are also some events that can cause interrupts in single-chip microcomputers. There are 5 in 8031: two external interrupts, two counter/timer interrupts, and one serial port interrupt.

Second, the nesting and priority processing of interrupts: Imagine that we are reading a book, the phone rings, and someone presses the doorbell at the same time. What should you do first? If you are waiting for an important call, you generally won't pay attention to the doorbell. On the contrary, if you are waiting for an important guest, you may not pay attention to the phone. If it is neither of these two (i.e. not waiting for a call, nor waiting for someone to come to the door), you may handle it according to your usual habits. In short, there is a priority problem here, and the same is true in the microcontroller, there is also a priority problem. The priority problem not only occurs when two interrupts are generated at the same time, but also occurs when one interrupt has been generated and another interrupt is generated, such as when you are answering the phone and someone presses the doorbell, or when you are opening the door to talk to someone and the phone rings. Consider what we would do.

Third, the interrupt response process: When an event occurs, before entering the interrupt, we must first remember which page of the book we are reading, or take a bookmark and put it at the current page, and then go to handle different things (because after handling, we have to come back to continue reading): when the phone rings, we have to go to the place where the phone is placed, and when the doorbell rings, we have to go to the door. These are also different interrupts, and we have to handle them in different places, and this place is usually fixed. This method is also used in computers. There are five interrupt sources. After each interrupt is generated, go to a fixed place to find the program to handle this interrupt. Of course, before going, you must first save the address of the instruction to be executed next, so that after handling the interrupt, return to the original place and continue to execute the program. Specifically, the interrupt response can be divided into the following steps: 1. Protect the breakpoint, that is, save the address of the next instruction to be executed, that is, send this address to the stack. 2. Find the interrupt entry, according to the interrupts generated by 5 different interrupt sources, find 5 different entry addresses. The above work is automatically completed by the computer and has nothing to do with the programmer. The interrupt handler is stored at these 5 entry addresses (it is placed there when the program is written. If the interrupt handler is not placed there, it is wrong and the interrupt handler cannot be executed). 3. Execute the interrupt handler. 4. Interrupt return: After executing the interrupt instruction, it returns to the main program from the interrupt location and continues to execute.

How does the microcontroller find the location of the interrupt program and how does it return? We will talk about this later.

The structure of the MCS-51 interrupt system:

As shown in the figure (sorry, please find a 51 book to look at this figure), it is composed of special function registers related to interrupts, interrupt entries, sequential query logic circuits, etc., including 5 interrupt request sources, 4 registers IE, IP, ECON and SCON for interrupt control to control the interrupt type, interrupt on and off and the priority determination of various interrupt sources.

Interrupt request source:

(1) External interrupt request source: external interrupt 0 and 1, introduced through external pins. There are two pins on the microcontroller, named INT0 and INT1, which are P3.2 and P3.3. There are four bits in the internal TCON that are related to external interrupts.

IT0: INT0 trigger mode control bit, which can be set and reset by software. When IT0=0, INT0 is low level trigger mode, and when IT0=1, INT0 is negative transition trigger mode. The difference between these two modes will be discussed later.

IE0: INT0 interrupt request flag. When there is an external interrupt request, this bit will be set to 1 (this is done by hardware). After the CPU responds to the interrupt, IE0 will be cleared to 0 by hardware.

The purpose of IT1 and IE1 is the same as that of IT0 and IE0.

(2) Internal interrupt request source

TF0: overflow interrupt flag of timer T0. When T0 counts and overflows, TF0 is set by hardware. When the CPU responds to the interrupt, TF0 is cleared by hardware.

TF1: Similar to TF0.

TI, RI: serial port send and receive interrupts, which will be explained in the serial port.

2. Interrupt enable register IE

In the MCS-51 interrupt system, the enabling or disabling of interrupts is controlled by the on-chip bit-addressable 8-bit interrupt enable register IE.

Where EA is the master switch, if it is equal to 0, all interrupts are not allowed.

ES - Serial port interrupt enable

ET1 - Timer 1 interrupt enable

EX1 - External interrupt 1 interrupt enable.

ET0 - Timer 0 interrupt enable

EX0 - External interrupt 0 interrupt enable.

That is 8CH. Of course, we can also use bit operation instructions

SETB EA
SETB ET1

SETB EX1

to make it happen.

3. Natural priority of five interrupt sources and interrupt service entry address

External interrupt 0: 0003H

Timer 0: 000BH

External interrupt 1: 0013H

Timer 1: 001BH

Serial port: 0023H

Their natural priority is from highest to lowest.

At this point, you should understand why we wrote some programs like this:

ORG 0000H

LJMP START

ORG 0030H

START:

The purpose of writing in this way is to make the vector address occupied by the interrupt source. Of course, when there is no interrupt in the program, it is not wrong to write the program directly from 0000H in principle, but it is best not to do so in actual work.

Priority: The microcontroller adopts a strategy of natural priority and manually set high and low priority, that is, the programmer can set which interrupts are high priority and which are low priority. Since there are only two levels, there must be some interrupts at the same level. Those at the same level are determined by natural priority.

When the computer is powered on, each interrupt is at a low priority. We can use instructions to set the priority. See Table 2

The interrupt priority is set high by the interrupt priority register IP. If a bit in IP is set to 1, the corresponding interrupt is of high priority, otherwise it is of low priority.

Example: Suppose the following requirement is to set T0 and external interrupt 1 to high priority and the others to low priority. Find the value of IP.

The first 3 bits of IP are useless and can be any value, set to 000, and then write according to the requirements.
Therefore, in the end, the value of IP is 06H.

Example: In the above example, if 5 interrupt requests occur at the same time, find the order of interrupt response.

The response order is: timer 0->external interrupt 1->external interrupt 0->real-time device 1->serial interrupt.

MCS-51 interrupt response process:

1. Interrupt response conditions: At this point, we still feel amazed at the computer's response to interrupts. We humans can respond to external events because we have multiple "sensors" - eyes and ears that can receive different information. How do computers do this? In fact, it is not surprising at all. When MCS51 is working, it will check each interrupt flag in each machine cycle to see if they are "1". If they are 1, it means that there is an interrupt request. So the so-called interrupt is actually a query, but it is checked every cycle. For a human, this is equivalent to looking up every second when you are reading a book to check whether someone is ringing the doorbell or whether there is a phone call. . . . Very stupid, isn't it? But computers are like this. They are not smart at all.

After understanding the above interrupt process, it is not difficult to understand the conditions for interrupt response. In one of the following three situations, the CPU will block the response to the interrupt:

The CPU is processing an interrupt request of the same or higher level.

The current machine cycle is not the last cycle of the currently executed instruction. We know that the microcontroller has single-cycle, double-cycle, and triple-cycle instructions. It doesn't matter if the currently executed instruction is a single byte. If it is a double-byte or quad-byte, you have to wait until the entire instruction is executed before responding to the interrupt (because the interrupt query can be found in every machine cycle).

If the currently executed instruction is a return instruction (RETI) or an instruction accessing IP or IE registers, the CPU should execute at least one more instruction before it should be interrupted. These are all related to interrupts. If IP or IE is being accessed, the interrupt may be turned on or off or the interrupt priority may be changed. The interrupt return instruction indicates that the interrupt has not been processed yet, so you have to wait until the processing of this instruction is completed and then execute another instruction to respond to the interrupt.

2. Interrupt response process

When the CPU responds to an interrupt, it first puts the address of the next instruction of the current instruction (that is, the instruction to be executed after the interrupt returns) into the stack, and then according to the interrupt flag, puts the corresponding interrupt entry address into the PC. The PC is the program pointer. The CPU fetches instructions based on the value in the PC. The value in the PC determines where to fetch instructions, so the program will jump to the interrupt entry to continue execution. All these tasks are completed by hardware, so we don't have to consider them. There is another question here. Have you noticed that each interrupt vector address is only separated by 8 units, such as 0003-000B. How to complete the interrupt program in such a small space? It's very simple. If you arrange an LJMP instruction at the interrupt, can't you jump the interrupt program to anywhere?

A complete main program should look like this:

ORG 0000H

LJMP START

ORG 0003H

LJMP INT0; transfer to external interrupt 0

ORG 000BH

RETI; Timer 0 interrupt is not used, so a RETI is placed here. In case an interrupt is "accidentally" generated, it will not have too serious consequences.

After the interrupt program is completed, a RETI instruction must be executed. After executing this instruction, the CPU will take out the address saved in the stack and send it back to the PC, so the program will continue to execute from the interruption point of the main program. Note: The protection work done by the CPU is very limited. It only protects one address, and all other things are not protected. Therefore, if you use A, PSW, etc. in the main program, and you want to use them again in the interrupt program, you must ensure that the data in the main program is still the data before the interruption after returning to the main program, so you have to protect it yourself.