Practical Power Management for Embedded Media Engines

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Practical Power Management for Embedded Media Engines [Copy link]

There are many power management techniques available and many new ones are being actively researched. Unfortunately, the most effective techniques often conflict with operating system and application frameworks. New techniques are often quite complex and optimized for specific specialized applications, and their applicability on general-purpose computing platforms is often limited. This article first summarizes common power saving techniques, then introduces some higher-payoff techniques (CPU clock idling and voltage and frequency scaling), and how these supporting technologies are integrated into auxiliary power manager modules to become real-time operating systems for digital signal processors (DSPs). An audio application example is provided to show how this architecture can be used to significantly improve power efficiency. This article is the first in a two-part series dedicated to low-power design. The second article will focus on peripheral and I/O power management techniques to extend power saving beyond the CPU core.

Power saving technology

The total power consumption of a CMOS circuit is the sum of active power consumption and static power consumption. Active power consumption occurs when the circuit is operating or switching from one logic state to another; static power consumption occurs when the circuit is not switching, mainly due to transistor leakage current. The approximate active power consumption is calculated as follows:

Pactive ~ Cpd x F x Vcc2 x Nsw

Here Cpd is the dynamic capacitance, F is the switching frequency, Vcc is the supply voltage, and Nsw is the number of bits converted. As can be seen from the above equation, the simplest way to save active power is to stop the circuit clocking, that is, set F to zero and let Pactive be zero. Many CPUs have "idle" or "stop" instructions to achieve this purpose, which gates the internal CPU clock off while the CPU is waiting for an interrupt. In addition, some processors include discrete controls that can gate off non-CPU clock domains such as caches, DMA, peripherals, clock pulse generators, etc.

Looking back at the equation above, if the application can still meet the processing requirements when the CPU clock rate is reduced, then the active power consumption can be saved proportionally. If the CPU frequency can be safely reduced, and that frequency is compatible with the lower operating voltage available to the CPU, then due to the quadratic relationship of Vcc, additional significant power savings can be achieved by reducing the voltage. However, reducing the CPU clock rate will also proportionally increase the time to execute the task, which requires careful analysis of the application to see if it can still meet real-time requirements.

Add power management support to the OS

Clock idling and dynamic frequency and voltage scaling have a huge impact on both the overall application and the operating system itself, which is often a barrier to implementing the above techniques. For example, if the CPU frequency is scaled dynamically, it may affect the OS time base and cause failures in peripheral drivers whose clocks are tied to the CPU clock. Similarly, if a task arbitrarily idles the CPU while waiting for I/O to complete, it can easily cause the application to deadlock. Therefore, in order to actively adopt the above techniques, the OS must be power aware and some operational responsibilities (such as CPU clock idling) must be borne by the OS.

Texas Instruments (TI)'s DSP/BIOS operating system adds a power manager module (PWRM) as an auxiliary module, as shown in Figure 1. The power manager is loosely connected to the OS kernel and sits alongside it; it is not another task in the system, but exists as a set of APIs that execute in the context of application control threads and device drivers.

Figure 1 Power Manager Partitions

Through the above APIs, the power manager supports voltage and frequency (V/F) scaling, frequency-only scaling, clock domain idling, automatic idling of configured clocks during OS idle time, and most importantly, the coordination of power events throughout the application (such as application code, drivers, and the OS itself), notifying registered clients when specific power events occur. Examples of power events are: frequency about to be scaled, frequency scaling completed, entering deep sleep state, waking from deep sleep state, low power, etc. Power management activities are application triggered; the main decision to change the DSP operating mode or function is made by the application, with help from calls to the power manager.

The PWRM interfaces directly with the DSP hardware by writing to the clock idle configuration registers and the platform-specific power scaling library (PSL) that controls the CPU clock rate and voltage regulation circuitry. The PSL isolates the PWRM and the rest of the application from the low-level implementation details of the frequency and voltage control hardware, ensuring safe transitions between supported voltage and frequency combinations (set points).

Audio Examples

A simple audio application was used as a test vehicle and as a benchmark to test the efficiency of the power manager features. The application was modified to measure the effect of activating different power saving features. Current sensing resistors were placed in series with the motherboard power supply and the DSP core power supply, and a voltmeter was used to measure the voltage drop across the resistor to determine the current drawn by the motherboard and DSP core.

Conclusion

Taking a phased approach to implementing power management can significantly reduce power consumption. There is no need to wait for new technology research currently underway to bear fruit; in some cases, incorporating a few basic and practical key enabling technologies into the operating system or application framework can achieve CPU power savings of more than 95%. Power management support is designed in a way that is easy to use, allows developers to select specific technologies that meet specific application requirements, and is highly portable. The framework can serve as a springboard to prepare for the addition of new and more aggressive specialized technologies as they emerge and future power management technologies