Internal Hardware Resources of PIC 16F84 Microcontroller (Part 7)

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Internal Hardware Resources of PIC 16F84 Microcontroller (Part 7) [Copy link]

10 Reset
　　Reset is the initialization operation of the microcontroller. Its main function is to initialize the program counter PCL to 000H, so that the 16F84 microcontroller can start executing the program from unit 000H.
　　The PIC16F84 microcontroller has the following different reset modes.
　　(1) Chip power-on reset POR.
　　(2) Reset by adding a low level to the external MCLR pin in normal working state.
　　(3) Reset by adding a low level to the external MCLR pin in power saving sleep state.
　　(4) Reset by overflow of the watchdog timer WDT.
　　The PIC16F84 microcontroller has an integrated "power-on reset" POR circuit. For general applications, just connect the MCLR pin to a high potential.
　　To use MCLR reset in normal working or sleep state, just press a button on the MCLR pin and connect it to ground momentarily.
　　The reset operation of the microcontroller 16F84 will affect some other registers, as shown in Table 1.

　　11. Watchdog timer WDT
　　MCU systems are often used in industrial control. There are usually various interferences at the operation site, which may cause the execution program to bounce into an infinite loop, thus paralyzing the entire MCU control system. If the operator is present, he can manually reset the system to get rid of the infinite loop. However, the operator cannot monitor the system all the time. Even if he monitors the system, he often performs a manual reset only after causing adverse consequences. Since the PIC16F84 MCU has an automatic program operation monitoring system, the watchdog timer WDT (Watch Dog Time), literally translated as "watchdog" timer. This is like an owner raising a dog. When the owner is working normally, he always remembers to feed the dog at regular intervals, so the dog stays quiet and does not affect the owner's work. If the owner takes a nap and stops working, at a certain time, the dog is hungry and finds that the owner has not given it food, it will bark and wake up the owner. It can be seen that WDT has the following characteristics:
　　(1) It can work independently and basically does not rely on the CPU.
　　(2) The CPU communicates with the WDT once at a fixed time interval (such as clearing it, that is, feeding the dog once) to indicate that the system is currently working normally.
　　(3) When the CPU falls into an infinite loop, it can be detected by the WDT in time (such as WDT count overflow) and the system is reset.
　　The pulse sequence of the timing count of the WDT in the PIC16F84 microcontroller is generated by an independent RC oscillator on the chip, so it does not need any external devices to work. Moreover, this on-chip RC oscillator is independent of the oscillation circuit on OSC1/CLKIN (pin {16}). Even if the clocks on OSC1 and OSC2 are not working, the WDT can still monitor the timing. For example: when the PIC16F84 executes the SLEEP instruction, the chip enters the sleep state, the CPU does not work, and the main oscillator stops working, but the WDT can still monitor the timing. When the WDT timeout overflows, the chip can be activated (wake up) to continue normal operation. During normal operation, the WDT timeout overflow will generate a reset signal. If this monitoring timing function is not needed, this function can be turned off during firmware programming. The attached figure is a block diagram of the monitoring timer. Table 2 shows the registers related to WDT.
　　The basic timing time of WDT is 18ms without adding a divider. This timing time is also affected by temperature, VDD and process parameters of different components. If a longer timing period is required, the pre-divider can be configured to WDT through software control of the OPT/ON register. The maximum division ratio of this pre-divider can reach 1:128. In this way, the timing period can be expanded by 128 times, that is, 2?3 seconds. If the pre-divider is configured to WDT,
　　the CLRWDT and SLEEP instructions can be used to clear the WDT and the pre-divider at the same time, thereby preventing the timing overflow from causing a chip reset. Therefore, under normal circumstances, a CLRWDT instruction must be executed before each timing overflow (i.e., feeding the "dog" once) to avoid causing a chip reset. When the system is severely disturbed and is in an out-of-control state, it is impossible to execute a CLR WDT instruction before each timing overflow. The WDT will generate a timing overflow, thereby causing the chip to reset and re-enter the normal operation state from the out-of-control state.
　　When the WDT timer overflows, the D4 bit T0 in the status register will also be cleared. By detecting the T0 bit, it can be determined whether the reset is caused by the WDT timer overflow.