Internal Hardware Resources of PIC Microcontroller 16F84 (VI)

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Internal Hardware Resources of PIC Microcontroller 16F84 (VI) [Copy link]

8 Interrupt
　　PIC 16F84 has real-time processing function, and can handle abnormal events in the outside world in a timely manner by interrupt technology.
　　When the CPU of the microcontroller is processing an event, if an external event occurs (such as timer overflow, level change on the pin), the CPU is requested to process it quickly, so the CPU temporarily suspends the current work and turns to process the event. After the interrupt handles the event, it returns to the place where it was originally suspended and continues to perform the original work, as shown in Figure 1. The component that implements this function is called an interrupt system. The request source that generates an interrupt is called an interrupt source. The processing request made by the interrupt source to the CPU is called an interrupt request or interrupt application. The process in which the CPU temporarily interrupts its own affairs and turns to handle events is called the interrupt response process of the CPU. The entire process of handling events is called interrupt service (or interrupt processing). After the processing is completed, it returns to the place where it was originally suspended, which is called interrupt return.
　　The PIC16F84 microcontroller chip has 4 interrupt sources, and its logic circuit is shown in Figure 2.

　　9? Interrupt control
　　Interrupts are mainly controlled by the interrupt control register INTCON (Figure 3). INTCON is a read/write register that contains various enable controls and flags such as timer TMRO overflow, RB port changes, and external INT pin interrupts.
　　When the global interrupt enable bit GIE (D7) is set to 1, all unmasked interrupts will be enabled. If the bit is cleared to 0, all interrupts will be disabled. When responding to an interrupt, the GIE bit will be cleared to disable other interrupts, the return breakpoint address will be pushed onto the stack for protection, and then the interrupt entry address 0004h will be loaded into the program counter PC. In the interrupt service routine, by querying the interrupt flag bit, it is determined that the interrupt flag bit must be cleared by software before reopening the interrupt to avoid repeated interrupt requests.
　　(1) INT interrupt. The external interrupt on the RBO/INT pin is edge-triggered. When the INTEDG bit (bit 6 of the OPTION register) is set to 1, the rising edge is selected for triggering. If the bit is cleared to 0, the falling edge is selected for triggering. When a specified valid edge is detected on the pin, the INTE bit (bit D4 of INTCON) is set to 1. Before reopening this interrupt, the INTE bit must be cleared in the interrupt service routine. (2) TMRO interrupt. When the counter of timer TMRO overflows (i.e. changes from FFH to 00H), the hardware automatically sets TOIF (D2 bit of INTCON) to 1. The interrupt can be controlled by setting TOIE (D5 bit of INTCOND) to 1 or clearing it to 0.
　　(3) PORTB pin level change interrupt. Once there is a level change on the D7~D0 pins of the PORTB port, RBIF (D0 bit of INTCON) will be set to 1. This interrupt can be controlled by setting RBIE (D3 bit of INTCON) to 1 or clearing it to 0.
　　(4) Interrupt context protection. When an interrupt occurs, only the return breakpoint address is pushed onto the stack for protection. If the user also wants to protect key registers (such as the W register and the STATUS register), this needs to be implemented by software. For interrupt context protection, please refer to the example of PIC microcontroller instruction reading in the 15th issue of this newspaper.