Internal Hardware Resources of PIC 16F84 Microcontroller (Part 2)

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Internal Hardware Resources of PIC 16F84 Microcontroller (Part 2) [Copy link]

3 Data memory
　　In the PIC16F84 microcontroller, in addition to the program memory for storing programs, there is also a data memory. When executing a program, the microcontroller often needs to input some data to the microcontroller at any time, and some data may change at any time. In this case, a data memory is needed. Since the data memory must not only be able to read the data stored in its various units at any time, but also write new data at any time, or rewrite the original data. Therefore, the data memory must be composed of a random access memory RAM. When the RAM memory is powered off, the stored data is immediately lost, which sometimes brings inconvenience in practical applications. However, there is a 64×8-bit E2PROM data memory in the 16F84 microcontroller. The data stored in the E2PROM will not be lost when the power is off.
　　The RAM data memory in the 16F84 microcontroller is shown in Table 1. The RAM is divided into two banks: Bank 0 and Bank 1. Each bank can directly transmit information using the internal bus, so they all work and address in register mode. These eight-bit registers can be divided into two parts: general registers and special registers. General registers store data, and special registers store information that controls the operation of the microcontroller. Each memory bank can be expanded to a maximum of 7FH (128 bytes). In each memory bank, special registers are arranged in the low address space, and general registers are arranged in the high address space.
　　General registers have a single usage, but special registers have their own uses. Here is a brief introduction to the more basic special registers.
　　(1) Program counter (PCL, PCLATH). The program counter PC is a counter that manages the program. The program counter of PIC16F84 is 13 bits wide, and the maximum addressable storage space is 8k×14 bits. In fact, 16F84 only uses the first 1k×14 bits (0000~03FFH) of the storage space. Because the program counter is 13 bits wide, and the special register is only 8 bits. Therefore, PC is composed of two special registers. The lower eight bits PCL are a read/write register (address 02H or 82H), while the high byte PCH (valid bit 5) cannot be directly read/written. It is transmitted to the high byte of the program counter through an 8-bit holding register PCLATH (address 0A or 8AH). When CALL or GOTO is executed to write PCL, the high byte of the PC value is loaded from the PCLATH register.
　　(2) Status register STATUS. The status register STATUS contains the status of the arithmetic logic unit ALU operation result (such as whether there is a carry, etc.), reset status and data storage bank selection bit. The settings of the relevant bits are shown in Table 2, and the functions are as follows:
　　1) Bit 0. Carry/borrow bit C. After executing addition and subtraction instructions
Table 2　　
　IRP RP1 RP0 TO PD Z DC C
, if the result has a carry or borrow, C is set to 1, otherwise it is set to 0. This bit is also used when executing shift instructions.
　　2) Bit 1. Auxiliary carry/borrow bit DC. After executing the addition and subtraction instructions, if there is a carry or borrow from the lower four bits of the result to the upper four bits, DC is set to 1, otherwise it is set to 0.
　　3) Bit 2. Zero flag. If the result of the operation is zero, Z is set to 1; if the result of the operation is not zero, Z is cleared.
　　4) Bit 3. Low power flag PD. Set to 1 after power-on reset or execution of the CLRWDT instruction, and cleared after execution of the SLEEP instruction.
　　5) Bit 4. Timer time-out flag TO. Set to 1 after power-on reset or execution of the CLRWDT or SLEEP instructions, and cleared when the watchdog timer time-out.
　　6) Bits 5 and 6 (RP0, RP1). These two bits are used for register bank selection during direct addressing. That is, 00 - select Bank0 (00H~7FH); 01 - select Bank1 (80H~FFH). 16F84 has only two storage banks. Therefore, 10 and 11 are not used.
　　7) Bit 7 IRP. This is the register selection bit for indirect addressing. 0 - Select Bank 0, 1 (00H ~ FFH), 1 - Select Bank 2, 3. 16F84 only has Bank 0, 1, so this IRP bit should be set to 0.
　　(3) Indirect addressing of INDF and FSR registers
　　The INDF register is not a physical register, but a logical function register (address 00H or 80H). When addressing the INDF register, it actually accesses the unit pointed to by the content of the FSR register, that is, the FSR register is used as an indirect register. FSR is called the "register selection" register, and its address is (04H or 84H). Indirect addressing of the INDF register itself will read the content of the FSR register. For example, when FSR = 00H, the data read from INDF by indirect addressing will be 00H. When writing to the INDF register using indirect addressing, although the write operation may affect the status word in STATUS, the written data is invalid.