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Dear experts,

I am studying electronics, but there is an experiment in our school that is the design of a digital frequency meter, which I have never encountered before, so I beg you to give me some guidance. I would be grateful.

index

1. The test frequency range is: 1Hz~1MHz.
2. The range is divided into three levels: Level 1: When the gate time is 1S, the maximum reading is 999.999KHz
Second gear: When the gate time is 0.1S, the maximum reading is 9999.99KHz
Level 3: When the gate time is 0.01S, the maximum reading is 99999.9KHz.
3. Display working mode: a. Use BCD seven-segment digital tube to display the reading.
b. Using memory display method
c. Blanking of meaningless high-order zeros.
Require
(1) Design a solution that meets the design requirements
(2) Design unit circuit
(3) Use EDA software to simulate each unit circuit and the overall circuit
(4 ) Use EDA software to implement the design on the ELB electronic course design experiment box
This post is from FPGA/CPLD
 

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