XCVU9P board design schematic diagram: 616-Dual FMC signal processing board based on 6U VPX XCVU9P+XCZU7EV high performance...

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XCVU9P board design schematic diagram: 616-Dual FMC signal processing board based on 6U VPX XCVU9P+XCZU7EV high performance... [Copy link]

1. Board Overview

The board is based on the 6U VPX standard structure, including an XCVU9P high-performance FPGA and an XCZU7EV FPGA for IO expansion interface, dual-channel HPC FMC expansion of high-speed AD, DA, fiber optic interface, etc. It is an ideal board for high-performance digital computing and fiber optic acceleration. Beijing Taisu Technology's board is fully industrial-grade chip to meet high and low temperature requirements.

2. Technical indicators of processing board

● The master FPGA is XCVU9P-2FLGA2104I; the slave FPGA model is XCZU7EV-2FFVC1156I;

● The main FPGA is equipped with 2 sets of DDR4, each with 64-bit width and 8GByte capacity; BPI flash loading method, capacity of 128MByte; 1 I2C E2PROM; 4 LED indicators;

● The main FPGA has two sets of FMC HPC connectors, both supporting LA, HA, HB, and 8 GTY interfaces;

● The main FPGA and VPX backplane P1 interconnect 16 GTYs, P2 interconnect 8 GTYs, and P3 interconnect 16 pairs of LVDS;

● Main FPGA, 1 QSFP28 is connected to the front panel, the data rate supports 25GbpsX4, and the clock supports 156.25MHz;

● Main FPGA, front panel J30J connector (J14), JTAG interface, two receive and two transmit GPIO_LVTTL3V3;

● 24 pairs of LVDS are interconnected between the master FPGA (bank70) and the slave FPGA XCZU7EV (bank68), and 2 GTY (H) X 4 are interconnected;

● From FPGA to VPX backplane P2 interconnects 8 GTHs, P3 interconnects 16 pairs of LVDS, and P6 interconnects 44 GPIO_LVTTL_3V3;

● 1 Gigabit Ethernet (PL side) and 1 RS422 (PL side) interconnection from FPGA to VPX backplane P6;

● From the PL end of the FPGA board: 1 set of DDR4, 64bit, 2GByte capacity; 4 LED indicators;

● 1 set of DDR4, 64bit, 2GByte capacity; 2x QFlash, 64MByte capacity each; 1 EMMC, 8GByte capacity; 1 SD card, 16GByte capacity; 1 msata interface;

● 1 debug RS232 (Uart0) from the PS end of the FPGA board, and 2 Can interfaces at connector J11;

● 1 USB3.0 and 1 DP interface are output from the PS end on the rear of the FPGA board (not used in the VPX solution);

● 1 Gigabit Ethernet RJ45 (PS end) from the FPGA front panel;

● From the FPGA front panel J30J connector (J14), 1 RS232 or RS422 (PS end), 2 receive and 2 transmit GPIO_LVTTL3V3; JTAG debug port;

● Hardware connection supports BPI mode loading from the slave FPGA to the master FPGA.

3. Software System

● Provide interface test procedures for the main FPGA, including DDR4, fiber aurora, PCIe, FMC and other interfaces;

● Provides bare metal interface test programs from FPGA, including DDR4, RS232, and Gigabit Ethernet interfaces.

4. Physical properties

● Size: 6U VPX board, size is 160X233.35mm.

● Supports conduction cooling, air cooling structure and handle installation.

● Operating temperature: 0℃～ +55℃, supports industrial grade -40℃～ +85℃

● Working humidity: 10%～80%

5. Power supply requirements

● DC power supply. The power consumption of the whole board is 120W.

● Voltage: +12V 10A, ripple: ≤10%.

● Support external independent power supply interface J8; support fan interface JP4, 12V.

6. Application fields

Software radio system, baseband signal processing, wireless simulation platform, high-speed image processing, fiber-optic accelerated computing, etc.

Fiber optic accelerated computing, baseband signal processing, high-performance digital computing card, high-speed image processing card, XCVU9P card