Classic voltage-to-current circuit design principle

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Classic voltage-to-current circuit design principle [Copy link]

Voltage-to-current circuits are very common in industrial environments. Next, I will introduce its principles and design examples.

1. High-side V/I circuit principle

This high-side voltage-to-current conversion circuit can well provide adjustable current for grounded loads. The circuit structure adopts a two-stage design. The first stage uses OPA+NMOS to convert VIN into a power reference signal to drive the second stage OPA. The second stage OPA adjusts the load current by controlling the gate of PMOS.

The circuit's VI transfer function is derived from the relationship between the input voltage VIN and the three current sensing resistors RS1, RS2, and RS3.

The relationship between VIN and RS1 determines the theoretical first stage current:

VRS1=VIN

The current gain from the first stage to the second stage depends on the relationship between RS2 and RS3:

IRS2 is approximately equal to IRS1, VRS3 is approximately equal to VRS2, ILOAD is approximately equal to IRS3

Final load current formula:

2. Design Case:

Set the target: 5V power supply, VIN varies between 0~2V; Vout is 4.5V/0~100mA, and the efficiency should reach 98%.

Power supply voltage: 5V DC

Input voltage range: 0~2V DC

Output voltage: 4.5V/0~100mA DC

Efficiency: 98%

Gain error: 0.1%

2.1. Design RS1:

Note that the first stage circuit cannot provide power to the load, so the energy consumption generated by the current of the first stage circuit will directly affect the efficiency of the entire system. Therefore, we limit the power consumption of the first stage to 1% of the full-scale output current to ensure that the efficiency target of 98.5% is achieved, and sufficient space should be left for the quiescent current of the operational amplifier. Therefore, when the output is full-scale 100mA, the design should set the current in the first stage IRS1 to 1mA.

VRS1=VIN = 2V

RS1 = VIN ÷ IRS1 = 2V ÷ 1mA = 2KΩ

>>> IRS2 ≈ IRS1 = 1mA b. Design RS2/RS3:

The second stage of this circuit is mainly responsible for generating output current to drive the load. Since A2's IN+≈IN-, VRS3≈VRS2. Considering that we use a 5V power supply and hope that Vout=4.5V, VRS3 needs to be below 500mV at full scale. Assuming that Q2's voltage drop is 0.3V, VRS3 is 470mV.

RS2 = VRS3 ÷ IRS2 = 470mV ÷ 1mA = 470Ω

RS3 = VRS3 ÷ ILOAD = 470mV ÷ 100mA = 4.7Ω

c. Op amp compensation design: R2/R3/C6/R4/R5/C7

Compensation components need to be added in both stages to ensure that the circuit can operate stably. When the operational amplifier drives a capacitive load (MOS parasitic Cgs), it is easy to generate output oscillation, and the circuit structure after compensation is the classic operational amplifier dual feedback loop. For details, please refer to the dual feedback design below.

Operational Amplifier Stability—Dual Feedback Loop

2.2. Device selection:

1. Operational amplifier: It is best to choose one with low offset voltage and temperature drift.

2. MOSFET: To ensure that OPA can control the gate, it is recommended to select a low threshold voltage VGS(th). In addition, VGS, GSDS, and ID cannot exceed the rated value.

3. Resistor selection (accuracy requirements): The three resistors RS1, RS2, and RS3 as the circuit transfer function have a great impact on the output current accuracy. If the gain error design target of 0.1% FSR is to be met, the tolerance of these resistors should be 0.1%. This is because the first-stage current will be multiplied by the ratio of RS2 and RS3 in the second stage. Therefore, the design accuracy of the first stage is particularly important because the error in the second stage will be doubled and transmitted to the output. Therefore, if you want to improve accuracy, you may also need to reduce the tolerance of the RS1 resistor. There is a problem with the service, please try again later.

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beyond_笑谈

"The tolerance of these resistors should preferably be 0.1%"

The comprehensive error of resistors in actual circuit boards cannot be guaranteed to be 0.1%

Maker_kun

What are the main application scenarios?