Domestic Tang Primer 25K evaluation using Gaoyun SDRAM IP core to drive the official SDRAM expansion board encountered problems

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Domestic Tang Primer 25K evaluation using Gaoyun SDRAM IP core to drive the official SDRAM expansion board encountered problems [Copy link]

 

1. I bought an official SDRAM development board before, and found that Gaoyun has an SDRAM IP core, so I planned to use the IP core and write a controller module for it to simply display a picture. I chose a color bar picture like the following
   
   


2. Then I used the example given by Gaoyun to test. After using the SDRAM Controller GW2AR-18 RefDesign reference design project for simple parameter adaptation, I downloaded it for observation and got the waveform as follows:
   
   
   
   I found that the data written to SDRAM was inconsistent with the data read from SDRAM. Only the first bit of the data read out was consistent with the input data. Moreover, only one data was automatically read out from SDRAM each time, and its duration was the total burst data length. This was inconsistent with the user read and write timing diagram in the Gaoyun IP manual I saw.


3. The waveforms in Gaoyun User Manual are as follows: Obviously they are not consistent and the difference is obvious
   
   

I set the parameters of the IP core as follows:
sdram_clk / sdrc_clk =100MHz,
CAS = 4'd2T_WR = 4'd2
T_MRD= 4'd2
T_RP = 4'd1
T_RCD= 4'd1
T_RC = 4'd4

DATA_WIDTH = 16ROW_WIDTH = 13,
COL_WIDTH = 8,
BANK_WIDTH = 2,

1. Now I suspect that the SDRM chip is broken... (because I did have a brain glitch and inserted it backwards), or the official SDRAM IP core cannot drive the SDRAM chip model W9825G6KH-6, or the Gaoyun official reference routines are just as I downloaded and grabbed, and cannot read and write continuous data, so how can I change it? I tried to change it several times but it didn't work.

1. I want to ask if anyone has this development board and SDRAM expansion board? Use software to grab the data to see if it is consistent with mine?

Jacktang

I suspect the SDRM chip is broken.

The question is how did it break? What is the reason? Can it be avoided in the future?

Help the landlord to top

littleshrimp

You used the routine of 18 to change it to 25. There may be a configuration error in the process. Can you send the modified routine to see if other netizens who have this board can help you try it? In addition, you can also buy an SDRAM and try it to see if it is plugged in the wrong way and it is damaged.

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littleshrimp posted on 2024-3-5 16:29 You are using the 18-bit routine to change it to 25-bit. There may be a configuration error in the process. Can you post the modified routine to see other websites with this board...

The SDRAM board is a bit expensive, and students are reluctant to make a hasty decision. I will post the program

viva_xin

You can do an experiment where the written data keeps changing until busy is pulled up, and then see what the actual read result is.

One more question, are the timing parameters of the IP core officially provided?

littleshrimp

Xuexuexuexuexuexue published on 2024-3-5 22:12 SDRAM board is a bit expensive, students are reluctant to judge it easily, I will send you the program

W9825G6KH-6 Taobao 2.5 yuan free shipping

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viva_xin posted on 2024-3-5 22:26 You can do an experiment, the written data will keep changing until the busy is pulled up, and then see what the actual read result is. Another question...

The captured image I posted above has this situation. The parameters are the parameters in an official routine, but that routine does not use IP and is written directly to the driver. I have tried using the official default parameters, but it doesn't work.

guczw

sdram_clk, sdrc_clk, the I_sdrc_clk phase needs to be set in the PLL, for example, 22.5 degrees, the two form a phase difference: "When the SDRAM controller works at a high rate, it is necessary to adjust the I_sdrc_clk phase to meet the setup/hold time of the read and write signals on the SDRAM side."

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Jacktang posted on 2024-3-5 07:56 I suspect the SDRM chip is broken. The question is how did it break? What is the reason? Can it be avoided in the future? Please give a thumbs up to the original poster

It has been solved. It was found that the main problem was the clock.