SiC FET — A “totem” symbol?

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SiC FET — A “totem” symbol? [Copy link]

The totem pole power factor correction circuit has long been an idea, and many engineers have searched for the technology to implement it effectively. Now, it has been discovered that SiC FETs are the ideal switches to maximize the benefits of this topology. Learn how.

We don’t know who coined the term “bridgeless totem pole power factor correction stage,” but it must have been born out of some brilliant, inspired moment. In an AC/DC power supply, this circuit enables power factor correction, effectively improving efficiency by up to 2% in low-line applications by eliminating the need for an AC line bridge rectifier. We’ll look at this further below and will refer to it as “TPPFC” for brevity.

Ideal switch required

The TPPFC architecture was first demonstrated around 2011, and by using ideal switches and low-loss magnetics, the circuit could theoretically achieve 100% efficiency. This was a futuristic idea, however, as the semiconductors used to make high-frequency boost switches have been less than ideal to date. The problem is the trade-off between conduction losses and switching losses. To reduce on-resistance and conduction losses, we need to increase the effective die area, but this increases device capacitance and dynamic losses. Another problem is that the TPPFC must operate in a “hard-switched” continuous conduction mode above moderate power levels to keep the peak current controllable, and this requires restoring the charge stored in the body diode of the switch. When using silicon MOSFETs, the charge is quite large and the resulting dissipation is high, making any small net gain in the circuit insignificant, especially considering the cost and complexity of the switch drive and control.

Using wide-bandgap semiconductors helps us achieve our goals

While a 2% theoretical efficiency gain is very attractive, server efficiency standards such as the “80+Titanium standard” require an AC/DC power supply with only 4% total end-to-end losses at 230VAC and 50% load.

Figure 4: Si/SiC cascode

Since 2% is usually allocated to the AC front end, the TPPFC must be re-engineered with new technologies to improve its performance, and this has changed with the development of wide bandgap switches. Silicon carbide and gallium nitride are both candidate technologies, with SiC MOSFETs having an 80% lower reverse recovery current compared to silicon, while GaN has no reverse recovery current. In addition, their output capacitance is lower than that of silicon MOSFETs because WBG die are generally smaller than silicon die at the same voltage level. This is due to the WBG material having a higher critical electric field, a thinner voltage support area required to handle the same peak voltage, and higher doping, resulting in lower on-resistance. The low-loss advantages of SiC and GaN can be summarized in the figures of merit R DS(on) x A and R DS(on) x E OSS , the former representing the trade-off between on-resistance and die area, and the latter representing the trade-off between on-resistance and switching losses caused by output capacitance.

WBG devices make the TPPFC stage possible, and the related circuits are now popular, but they are not perfect, because the significant advantages of SiC and GaN also hide some practical problems. It is undeniable that the recovery charge of SiC MOSFET is low, but the forward voltage drop of the body diode is very high, which will add some additional losses. In addition, the gate drive is sensitive to threshold hysteresis and variability, and the high voltage required to achieve full boost is also very close to the absolute maximum, which is very dangerous. In contrast, GaN devices have a lower gate voltage threshold, so there may be a risk of stray and catastrophic turn-on during switching transients. This can be alleviated by setting the turn-off drive voltage to a negative value, but it will cause a very high voltage drop during the reverse conduction of the device before the channel is enhanced, which will increase losses. And the cost of GaN is still relatively high.

SiC FETs – Perfection

However, there is another option, known to semiconductor manufacturers for decades, called “cascode” technology, which combines a high voltage switch with a low voltage switch to achieve conduction loss and switching loss advantages. In products using wide bandgap, a normally-on SiC JFET is paired with a low voltage silicon MOSFET to obtain a normally-off device with non-critical gate drive, a low-loss body diode, and all the advantages of a WBG device. The “SiC FET” offered by UnitedSiC uses this design approach to achieve very fast switching speeds, as well as a small die size for low capacitance and low dynamic losses.

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Read the original article: https://www.eeworld.com.cn/zt/Qorvo/view/1400