Analyzing the role of capacitive load compensation in DDR design

yvonneGan

Analyzing the role of capacitive load compensation in DDR design [Copy link]

This post was last edited by yvonneGan on 2023-5-16 18:09

Mr. High Speed member--Sun Xiaobing

Let's first understand the impact of capacitive load and inductive load on link impedance. The simulation link model is shown in the figure below. There are three sections of 50Ω ideal transmission lines in the link. A capacitor is added between the first and second sections to simulate the capacitive load, and an inductor is added between the second and third sections to simulate the inductive load. At the end of the link is a 1KΩ resistor, which is equivalent to an open circuit. Use the TDR simulation tool to view the impedance of the entire link.

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Here is a brief introduction on how to read the impedance curve results. The horizontal axis of the coordinate represents time, corresponding to the position points of the transmission line at different transmission times when viewed from one end, and the vertical axis of the coordinate represents the impedance value. From the impedance curve below. The impedance of the link changes when the transmission is 1ns, and the transmission delay of the first section of the transmission line in the link is 0.5ns. Why does the time scale not correspond? The reason is that the method of viewing the time domain impedance of the link is to compare the input voltage and the reflected voltage amplitude through the principle of signal reflection. The pulse signal needs a back and forth process. Therefore, the time point in the impedance curve is actually twice the transmission line delay.

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From the link impedance curve results above, the capacitive load causes the link impedance to drop instantly, and then slowly rises and returns to the original line impedance. The inductive load causes the link impedance to rise slowly first, and then slowly returns to the link impedance. For the capacitive and inductive mutations in the link, the impedance change felt by the signal does not only exist for a moment, but changes over time.

After understanding the impact of capacitive load and inductive load on link impedance in the link, let's take a look at the impact of capacitive load on link impedance in the DDR Fly_By design link. The following is a common DDR one-to-five Fly_By topology design, where one master controller drags five load particles in the link, and the termination resistor is placed behind the last particle.

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Let's first compare the signal quality of the front-end particles in the DDR link before and after capacitive load compensation, because for the Fly_By link, the signal quality of the front-end particles is the worst. The following figure is the signal eye diagram obtained by simulating the front-end particles in the link with and without capacitive load compensation.

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(, downloads: 0) From the above simulation results, when there is no capacitive load compensation, the signal eye height of the front-end particle receiving is 193mV, and after the capacitive load compensation, the signal eye height increases to 303mV. Therefore, in a multi-load link, capacitive load compensation can significantly improve the load signal quality.

So what effect does capacitive load have on the link? How to compensate for capacitive load? Why can capacitive load compensation improve the signal quality on the link? The following is an explanation through observation and analysis of link impedance.

The S parameters of the branch lines in the above link before and after capacitive load compensation are extracted respectively. The TDR details of the link are shown in the simulation software as follows. The detection point is selected at the master end. The blue curve is the link impedance without capacitive load compensation. The main impedance of area 1 is 40Ω, the impedance of the branch part is about 32Ω at the lowest, and the average impedance of area 2 is about 34Ω. The red curve is the link impedance result with capacitive load compensation. The impedance of the branch part tends to 50Ω at the beginning, but it will drop immediately. The impedance of the branch part is about 37Ω at the lowest, and the average impedance of area 2 is about 41Ω.

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From the above analysis of the pure link impedance results, it can be seen that the impedance felt by the signal at the branch part will be 6-10Ω lower than the actual routing impedance, and capacitive load compensation is to deliberately raise the impedance of the branch part to make the overall link impedance more matched.

Previously, we only considered the influence of branch stubs and vias. In addition to these influencing factors, chip package capacitance and die capacitance are also important factors affecting link impedance, which will lead to lower link impedance. Next, we will analyze the impact of adding chip parasitic capacitance to the link. Since the parasitic capacitance value of a general chip is roughly around 3pF, we hang a 3pF capacitor at each load position to simulate the impact of chip parasitic capacitance. The following is the link impedance curve result before and after adding chip parasitic capacitance.

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(, downloads: 0) From the above two impedance curve results, the influence of chip parasitic capacitance will cause the link impedance to be reduced by about 5Ω. Without capacitive load compensation, the impedance felt by the signal in the branch part is only 30Ω. For the link with capacitive load compensation, the impedance felt by the signal in the branch part is about 35Ω, which may be a large deviation from the 40Ω of the main road, but it is also closer.

The figure below is the impedance test result of a DDR one-to-three Fly_By link. The impedance of the main and branch lines is controlled at 50Ω, and no capacitive load compensation is performed. The green curve is the impedance test result of the bare board, and the red curve is the impedance test result with DDR particles attached. It can be seen that in the case of a bare board, the impedance of the branch part is 3Ω lower than the main road, and the influence of the particle package parasitic capacitance is added, and the impedance of the branch part is only 44Ω, which is 6Ω lower than the impedance of the main road.

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From the above test and simulation results, we can see that in a Fly_By link with multiple loads, due to factors such as branch stubs, parasitic capacitance of vias, chip packaging capacitance and die capacitance, the load is capacitive, so that the impedance felt by the signal in the branch part will be lower than the actual routing impedance. Capacitive load compensation is to increase the routing impedance of the branch part in advance, or reduce the impedance of the trunk line, to balance or offset the impact of the low impedance caused by the capacitive load, so that the overall impedance of the link is closer to matching, thereby improving the signal quality.

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The compensation capacitors can precisely match the bus load and produce perfectly offset charges to counteract the effects of other capacitors on the DDR bus, thereby reducing signal attenuation, reflections and distortion.

Analyzing the role of capacitive load compensation in DDR design [Copy link]

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