[Evaluation and experience of Zhongke Yihaiwei EQ6HL45 development platform] +06. Expansion interface-DAC test (zmj)

卿小小 · Published on 2022-11-14 16:24

[Evaluation and experience of Zhongke Yihaiwei EQ6HL45 development platform] +06. Expansion interface-DAC test (zmj) [Copy link]

This post was last edited by Qing Xiaoxiao on 2022-11-14 19:39

Zhongke Yihaiwei EQ6HL45 development platform evaluation experience] +06. Expansion interface-DAC test (zmj)

The Zhongke Yihaiwei EQ6HL45 development platform reserves three expansion interfaces J8/J12/J17.

In this test, the expansion interface J8 is connected to the DAC module, model AN9767. FPGA controls the DAC module to implement a signal generator design example using direct digital frequency synthesis (DDS) technology.

1. Hardware Description

1.1 Extension Interface

The Zhongke Yihaiwei EQ6HL45 development platform reserves three expansion interfaces J8/J12/J17.

//------Expansion interface J8/J12/J17
a. Expansion port J8 is a 40PIN (DIP-40 package) interface. There is 1 5V power supply, 2 3.3V power supplies, 3 grounds, and 34 IO ports. These IO ports are independent IO ports and are not reused with other devices. The IO port is connected to the FPGA pin and the level is 3.3V. Do not connect directly to a 5V device to avoid burning the FPGA. If you want to connect a 5V device, you need to connect a level conversion chip. A 33-ohm resistor is connected in series between the expansion port and the FPGA connection to protect the FPGA from damage caused by excessive external voltage or current.
b. Expansion port J12 is an 18-pin (DIP-18 package) camera interface. The power supply mode is 3.3V power supply. These IO ports are directly connected to the FPGA pins, and electrostatic protection should be paid attention to when using them.
c. Expansion port J17 is a 12-pin (DIP-12 package) interface, including 2 3.3V power supplies, 3 grounds, and 7 IO ports. These IO ports are directly connected to the FPGA pins, so you need to pay attention to electrostatic protection when using them.

1.2 DAC module AN9767

DAC module AN9767ADI AD9767 DAC chip, this chip is a dual-channel, 14-bit, 125Msps conversion rate high-performance DAC chip, supports I, Q output mode (this mode is often used in the field of digital communications). The output form is differential current output, and the output current full-scale range can be set to 2~20mA. The chip itself comes with a 1.2V reference voltage, and no external reference source is required.

//------DA约束（官方资料有误，以此为准）
a.通道DAC1：
DATA[13:00] = E3 D3 F4 E1 F5 F3 G6 F6 H6 H7 H4 H5 H7 H3
DAC1_CLK    = J6
DAC1_WRT    = K4
b.通道DAC2:
DATA[13:00] = L6 L3 N4 M5 P4 N3 U2 P3 L5 U1 K5 P2 N1 L2
DAC2_CLK    = L4
DAC2_WRT    = K3
//------UART约束
uart_rxd    = E16
uart_txd    = H12

2. Functional design

The project framework is shown in the figure:

2.1 Implementation

An example of a signal generator design that uses FPGA-controlled DAC modules to implement direct digital synthesis (DDS) technology.

By default, channel DAC1 outputs a sine wave;
By default, channel DAC2 outputs automatically switched sine, triangular, square, and sawtooth waves, with a switching frequency of 2 seconds, and the LED flashes as a switching indication.
The serial port controls the channel DAC2 to switch the output waveform. The effective instructions are 0xa0/0xa1/0xa2/0xa3, which output sine wave, triangle wave, square wave and sawtooth wave respectively.

The waveform data is the mif waveform file specified in the RAM or ROM. The FPGA reads the data in the RAM/ROM according to the address and outputs it to the DAC module. The DAC automatically completes the DDS waveform synthesis. When different RAM/ROMs are enabled, the DAC can output different waveforms.

2.2 Adding some IPs

This is the IP transaction record, for reference only.

Zhongke Yihaiwei's m4k can be set to either RAM mode or ROM mode, and the initial values of both can be set by formulating mif files.

The mif file is generated by the Mif Wizard/mif (coe) file generator and is provided in the attachment. It is mainly used to initialize the rom.

According to the DAC parameters, select the data width as 14 bits and the data depth as 1024.

2.2.1 PLL

After the system clock 50MHz is input into PLL, different frequencies are output to different logic functions. Among them, 125MHz is for DAC function and 50MHz is for serial port function. Other frequencies are reserved for testing.

2.2.2 Generate rom/ram from m4k

First, use the Mif Wizard/mif (coe) file generator to generate a mif file, where the data width is 14 bits and the data depth is 1024.

Then add the m4k IP. The IP type can be RAM or ROM. When actually using it, pay attention to the module instantiation reference and avoid errors.

//------mif file (sine wave, triangle wave, square wave, sawtooth wave)
sine_wave_14w_1024d.mif
triangular_wave_14w_1024d.mif
square_wave_14w_1024d.mif
sawtooth_wave_14w_1024d.mif

Here we only use m4k_ram_1 of the sine wave sine_wave to illustrate:

3. Experimental Results

Channel 1/Channel 2 of the oscilloscope are connected to DAC1/DAC2 respectively. After power is supplied and the program is downloaded, the output waveform can be observed.

(Please ignore the oscilloscope's specs and the simplicity of the BNC cable; these are the only hardware I have available.)

//------Domestic oscilloscope
Model: FNIRSI-1014D
Parameters: 100MHz sampling rate, 1GSa/s bandwidth.
//------Cable
Model: BNC coaxial cable
Quantity: 2
//------Phenomenon
a. Channel 1 measures DAC1: sine wave.
b. Channel 2 measures DAC2: cyclically outputs sine wave, triangle wave, square wave, and sawtooth wave. The LED flashes as a switching indication. The switching time is 2 seconds.
(The operation of switching waveforms through the serial port is not recorded in the video, but the actual measurement is OK)

//------Actual test results (please see the video for detailed results)

05_J8-DAC

//------Project files (including mif tools and mif files)

dac9767_j8_prj_v1.zip (2.09 MB, downloads: 1)

Mif_Maker_V2.2.rar (14.93 KB, downloads: 1)

//------END

卿小小 · Published on 2022-11-14 16:24

There are some errors in the description of the pin assignment of the expansion interface J8 in the reference material, so this article is the main one.

lugl4313820 · Published on 2022-11-15 07:18

This waveform looks very good!