【Silicon Labs Development Kit Review 05】- Clock System Architecture

jone5

【Silicon Labs Development Kit Review 05】- Clock System Architecture [Copy link]

 

Clock system architecture

The high-speed clock of the development board is 38.4M, and the low-speed clock is 32.768KHZ. The chip can reach a maximum of 76.8M, which means that the high-speed clock can be doubled at most.

The entire chip supports the following 7 clock sources, and its CMU

The clock generated by the clock source is multiplied by the CMU (Clock Management Unit) and distributed to WDOG, LETIMER, RTCC, etc.

The following is the relevant clock tree.

After understanding the relevant clock tree, let's implement a timer program to let the serial port print "I am robot" once every 1s.

freebsder

38.4 doesn't seem to be used much, why do we use this frequency...