Non-volatile memory balancing method

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Non-volatile memory balancing method [Copy link]

Non-volatile memory is becoming more complex at advanced nodes, where price and speed, power, and utilization are becoming some very application-specific tradeoffs to decide where to place this memory.

NVM can be embedded in the chip or moved off-chip using various types of interconnect technologies. But this decision is more complex than it might initially appear. It depends on the process node and voltage, the type of NVM and what is stored in it, and the budget for the entire chip or system. The

highest-performing processors use the smallest process geometries, which in turn will place the highest demands on NVM. Some of the challenges facing NVM are the relative difficulty of scaling capacity at smaller geometries, and the need to implement higher voltages to program the cells. At finer process geometries, more die area may be required to support the capacity required for the additional processing cores, and additional manufacturing costs may be required to support the higher voltages.

It becomes a balancing act between the power/performance improvements of smaller geometries and how much memory can be embedded cost-effectively.

In non-volatile memory, as you get below 40nm, the cost of embedding it becomes very high, so you may end up using more SRAM internally , but then delegate the NVM to an external device. But when doing so, the challenge becomes having enough bandwidth performance to be able to execute in a power-efficient manner.

Some MCU companies are moving to external memory rather than internal memory and using higher performance octal NVM to do this.

One of the advantages of doing this is simplicity. As a result, bare NAND devices are trending towards solid-state drives and memory cards, and there are fewer and fewer requirements for devices that need to interface directly with bare NAND (excluding storage controllers).

With the increase in the diversity of devices on the SPI (Serial Peripheral Interface) bus, and the proliferation of high-speed SPI interfaces (particularly quad SPI, octal SPI, xSPI), it has become a very interesting bus to use in addition to booting and executing directly on the bus. This approach is evident in NXP's microcontroller series that do not have on-chip embedded memory.

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NVM can be embedded in the chip or moved off-chip using various types of interconnect technologies. But the decision is more complicated than it might first appear. It depends on the process node and voltage, the type of NVM and what is stored in it, and the budget for the entire chip or system.