MSP430G2553 clock system configuration

火辣西米秀

MSP430G2553 clock system configuration [Copy link]

The clock module of the MSP430G2553 microcontroller mainly includes:

Three clocks: auxiliary clock ACLK, main clock MCLK, subsystem clock SMCLK

Three clock sources: internal low-frequency clock source LFXT1, internal digitally controlled RC oscillator DCO, external low-frequency oscillator (need to solder a crystal oscillator)

Commonly used macro definitions:

#ifndef __DisableCalData

　　SFR_8BIT(CALDCO_16MHZ);

　　SFR_8BIT(CALBC1_16MHZ);

　　SFR_8BIT(CALDCO_12MHZ);

　　SFR_8BIT(CALBC1_12MHZ);

　　SFR_8BIT(CALDCO_8MHZ);

　　SFR_8BIT(CALBC1_8MHZ);

　　SFR_8BIT(CALDCO_1MHZ);

　　SFR_8BIT(CALBC1_1MHZ);

　　#endif

/*
Function: When the button is pressed, the system main frequency switches between VLO and DCO, and the system delay function is used to output pulses of approximately 1 Hz and 10 Hz
*/
#include <msp430g2553.h>

volatile u8 flag=0;

void inter_init()
{
P1DIR = BIT0; // Set P1.0 to output
P1DIR &=~ BIT3; // Set the IO port P1.3 corresponding to button 1 to input
P1IFG &=~ BIT3; // Initialize and clear the interrupt flag
P1IE |= BIT3; //P1.3 interrupt enable
P1IES |= BIT3; //Falling edge generates interrupt
P1REN |= BIT3;//Enable internal pull-up and pull-down resistors
P1OUT |= BIT3; //P1.3 is set to pull-up resistor: OUT = 1; REN = 1;
__enable_interrupt();//Turn on total interrupt
}

#pragma vector = PORT1_VECTOR //Fixed format, declare interrupt vector address, cannot be changed__interrupt
void Port1 (void)
{
P1IE &=~ BIT3; //Disable P1.3 interrupt enableP1IFG
&= BIT3;//Because only P1.3 is used, all other interrupt flags are cleared.

switch(P1IFG)
{
case BIT3: flag++;P1IFG=0;break; //Interrupt generated by P1.3default
: break;
}

__delay_cycles(1000);//DebounceP1IE
|= BIT3; //P1.3 interrupt enable
}

void main(void)
{
WDTCTL = WDTPW | WDTHOLD; //Disable watchdogIFG1
&=~OFIFG; //After the crystal oscillator contact is bad and causes an error, the OSCFault flag will be set to 1. This is a non-maskable interrupt.
//__bis_SR_register(SCG1 + SCG0); // Turn off DCO
inter_init();
while (1)
{
if(flag%2)
{
BCSCTL2 = SELM_0 + DIVM_3; // Main frequency selects DCO, divided by 8 (try using //BCSCTL2 |= SELM_0 + DIVM_3 here
, you will find that it cannot be switched
DCOCTL = CALDCO_1MHZ; //DCO selects 1MHZ
BCSCTL1 = CALBC1_1MHZ; //Set the basic clock register 1 to the setting when the clock is 1Mhz, usually used with DCOCTL
P1OUT ^= BIT0;
__delay_cycles(12500);//Delay 10hz
}
else{
BCSCTL3 |= LFXT1S_2; // Determine VLOC
BCSCTL2 |= SELM_3 + DIVM_3; // Select LFXT1CLK or VLOCLK, divided by 8
P1OUT ^= BIT0;
__delay_cycles(1500);//delay 1hz
}

}
}