TMS320F28335 Study Notes - Clock

火辣西米秀

TMS320F28335 Study Notes - Clock [Copy link]

When using an active crystal oscillator as an external clock source, the crystal oscillator circuit in the DSP chip will be bypassed, and the external clock signal is input to the DSP through the XCLKIN pin. The watchdog timer takes the OSCCLK signal as its input. The C28x core converts the input CLKIN signal into the SYSCLKOUT signal (this is the 150MHz signal we usually mention). SYSCLKOUT is mainly used to provide clock signals for some peripherals on the DSP chip. According to the speed of the peripherals, they are generally divided into peripherals that require a high-speed clock signal HSPCLK (as the name implies, high speed peripheral clock), such as EPWM, ADC, etc.; and peripherals that only require a lower signal frequency LSPCLK (as the name implies, low speed peripheral clock), mainly some serial devices, such as SCI, SPI, I2C, McBSP, etc. HSPCLK and LSPCLK are both obtained by allocating SYSCLKOUT, mainly by configuring the control bits of the register to achieve different frequency division factors. An example is as follows:

The default power-on value of HSPCLK is SYSCLKOUT / 2, that is, when SYSCLKOUT is 150MHz, HSPCLK defaults to 75MHz, so if you want the peripheral to work at the highest frequency, you must not forget to set these bits. In addition, if not configured correctly, the period of the timer in the peripheral, such as the PWM timer, will be multiple times misaligned with the expected one. The default value of LSPCLK is SYSCLKOUT / 4.

In the SysCtrlRegs.PCLKCR0, SysCtrlRegs.PCLKCR1, and SysCtrlRegs.PCLKCR3 registers, there are separate enable controls for each peripheral clock signal. For example, if we disable ECANBENCLK in SysCtrlRegs.PCLKCR0, the ECANB module will have no clock signal input, and its power consumption will be almost zero. (Why? Because the power consumption of CMOS circuits is mainly dynamic power consumption!)