McBSP Serial Interface Technology and Program Design of TMS320VC5410

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McBSP Serial Interface Technology and Program Design of TMS320VC5410 [Copy link]

1. DSP serial interface technology

　　DSP is a unique microprocessor that processes large amounts of information using digital signals. Its working principle is to receive analog signals and convert them into digital signals of 0 or 1. It then modifies, deletes, and strengthens the digital signals, and interprets the digital data back into analog data or actual environment formats in other system chips. It is not only programmable, but also has a real-time running speed of tens of millions of complex instruction programs per second, far exceeding general-purpose microprocessors. It is an increasingly important computer chip in the digital electronic world. Its powerful data processing capabilities and high operating speed are the two most commendable features.

　　Nowadays, embedded systems are rapidly developing towards low power consumption, low cost, small size, high performance and high speed. With the continuous maturity of serial interface technology, it has gradually met the above design requirements and become an important interface solution. Especially in digital signal processors, the importance of serial ports is more prominent. Almost all digital signal processors provide one or more serial interfaces, and with the upgrading of digital signal processors, the corresponding serial interfaces are constantly strengthened in function and improved in performance.

　　Compared with the parallel interface, the biggest advantage of the serial interface is that it reduces the number of DSP pins and reduces the complexity of the interface design. Generally, the serial interface provides full-duplex synchronous operation, and the input and output data are processed in a serial manner in bits. At present, major semiconductor manufacturers in the world have submitted many different serial protocols, some of which have become industrial standards. Typical serial protocols include: Serial Peripheral Interface SPI and Queue SPI (QSPI) of MOTOROLA (Austin, TX), PHILIPS (Sunnyvale, CA), and National Semiconductor's microbus (microwire).

　　Figure 1 is a typical SPI protocol. The SPI protocol uses a master-slave setting, where one of the interconnected devices is the master device and the other devices are slave devices. The interface connection mainly includes the following four signal lines:

　　(1) Serial data input signal line, namely MISO (Master InSlave Out);

　　(2) Serial data output signal line, namely MOSI (Master Out-Slave In);

　　(3) Shift clock signal line, i.e. SCK;

　　(4) Slave device chip select signal line, i.e. SS.

　　2. Multi-channel cache serial port of TMS320VC5410 - McBSP

　　1. Features of McBSP

　　TMS320V5410 is the second generation of low-power TMS320C5000 series fixed-point digital signal processor produced by TI. It provides three high-speed, full-duplex, multi-channel cache serial ports McBSP, each of which can support 128 channels at a speed of 100Mbit/s. McBSP expands the functions based on the standard serial interface, so it has the same basic functions as the standard serial interface:

　　(1) Full-duplex communication;

　　(2) It has two levels of buffered send and three levels of buffered receive data registers, allowing continuous data stream transmission;

　　(3) Provide independent frame synchronization pulses and clock signals for data transmission and reception;

　　(4) Ability to interface directly with industry-standard decoders, analog interface chips (AICs), and other serial A/D and D/A devices;

　　(5) Support external shift clock or internal frequency programmable shift clock.

　　In addition, McBSP has the following special features:

　　(1) Can be directly connected to compatible devices such as IOM-2, SPI, AC97, etc.;

　　(2) Support multi-channel sending and receiving, each serial port supports up to 128 channels;

　　(3) Optional serial word length, including 8, 12, 16, 20, 24 and 32 bits;

　　(4) Support μ-Law and A-Law data compression and expansion;

　　(5) When performing 8-bit data transmission, you can select LSB or MSB as the start bit;

　　(6) The polarity of the frame synchronization pulse and clock signal is programmable;

　　(7) The generation of internal clock and frame synchronization pulse is programmable and has considerable flexibility.

　　2. Access to McBSP registers

　　TMS320VC5410 contains 3 groups of multi-channel cache serial ports. Each group of multi-channel cache serial ports has 23 registers associated with it. In addition to RBR[1,2], RSR[1,2], and XSR[1,2], 15 of these registers are addressable registers. Due to the storage space limitation of data page 0, some registers must be accessed through sub-address addressing. SPSA_x is a sub-address register. To access a specified register, just write the corresponding sub-address into SPSA_x. Table 1 lists the sub-address registers of McBSP.

　　Table 1 McBSP sub-address register

　　

　　Suppose you want to set the transmit control register 2 (XCR2_1) of McBSP1. First, write the subaddress 0x0005 to the subaddress register (SPSA_1). At the same time, the memory unit 0x0049 is mapped to the transmit control register 2 (XCR2_1). Then, the read and write operations of the memory unit 0x0049 are equivalent to the operations of the transmit control register 2 (XCR2_1).

　　Example: Set the transmit control register 2 (XCR2_1) of McBSP1.

　　3.McBST SPI interface design

　　The clock stop mode of McBSP is compatible with the SPI protocol. When McBSP is set as the master device, the transmitter output signal (BDX) is used as the MOSI signal of the SPI protocol, and the receiver input signal (BDR) is used as the MISO signal of the SPI protocol. The transmit frame synchronization pulse signal (BFSX) is used as the slave chip select signal (SS), and the transmit clock signal (BCLKX) corresponds to the serial clock signal (SCK) of the SPI protocol. Since the receive clock signal (BCLKR) and the receive frame synchronization pulse signal (BFSR) are internally connected to the corresponding parts of the transmitter, these signals are not used in the clock stop mode. When McBSP is set as the master device, the SPI protocol connection is shown in Figure 2.

　　3. McBSP interface example

　　1. High-precision digital-to-analog converter MAX541

　　The MAX541 is a 16-bit serial input, voltage output digital-to-analog converter powered by a single +5V power supply. The DAC output is unbuffered, so it has a low supply current of only 0.3mA and a low drift error of 1LSB. The DAC output range is 0V to VREF. The MAX541 uses a 3-wire serial interface and is compatible with serial communication protocols such as SPITM/QSPITM/MICROWIRETM. The MAX541 can achieve a throughput rate of up to 500×10 3 samples/second, which meets the requirements of most applications. The MAX541 uses an 8-pin DIP or SO package. The description of each pin of the MAX541 is listed in Table 2.

　　Table 2 MAX541 pin description

　　2.McBSP and MAX541 interface circuit

　　The interface circuit between TMS320VC5410 and MAX541 is shown in Figure 3.

　　In order to achieve high resolution and high accuracy for MAX541, MAX873 can provide a high-precision +2.5V low-impedance reference voltage source. In order to eliminate high-frequency and low-frequency interference, a decoupling capacitor must be connected between the REF pin and the analog ground. Since the digital input DIN of AX541 is compatible with TTL/CMOS logic levels, it can be directly connected to the serial output BDX of TMS320VC5410. In addition, the analog ground AGND and the digital ground DGND must be strictly isolated. Finally, the analog ground and the digital ground are connected together on the AGND pin of MAX541 to form a star-shaped ground system. The voltage follower operational amplifier MAX495 is connected to the output of MAX541. Table 3 shows the corresponding relationship between the digital input code and the analog output voltage.

　　Table 3 MAX541 unipolar interface

　　The DSP's transmit frame synchronization pulse signal (BFSX) is used as the chip select signal (CS) of MAX541, and the transmit clock signal (BCLKX) is used as the serial clock input of MAX541. The timing of the MAX541 three-wire interface circuit is shown in Figure 4.

　　As shown in FIG4 , when the chip select signal CS changes from a high level to a low level, the serial data is shifted bit by bit into the input register in the chip at each rising edge of the serial clock in the order from the most significant bit to the least significant bit.

　　3. Software Design

　　The following example of generating a sawtooth wave is used to illustrate the software design between TMS320VC5410 and MAX541.

　　When McBSP is used as the master device of SPI communication, it provides the clock signal for the slave device and controls the data transmission process. The clock signal on the CLKX pin must be enabled during the data packet transmission. When there is no data packet transmission, the clock signal remains high or low according to the polarity adopted. Usually, a 10MHz clock signal is generated by the sampling rate generator of McBSP and output by the BCLKX pin as the serial clock input signal of MAX541. McBSP uses the BFSX pin to provide the chip select signal for MAX541, so the frame pulse generator must be set correctly to generate a frame synchronization pulse during each data packet transmission, that is, the first bit of the data packet transmission is changed to a valid state (in this case, it is a low level valid, depending on the chip select signal CS of MAX541), and then maintain the valid state until the data packet is sent. In addition, according to the SPI transmission protocol, the data transmission delay time (XDATDLY=01b) must be set correctly. As shown in Figure 4, after the frame synchronization pulse is valid, the serial data is sent after about one clock cycle. According to the timing diagram shown in Figure 4, select a suitable clock scheme for McBSP, that is, set the clock stop mode of McBSP. In this example, clock stop mode 3 (CLKSTP=10b, CLKXP=1) is used, and its clock scheme is shown in Figure 5.

　　Table 4 lists some register bits related to SPI settings.

　　Table 4 Register bits related to SPI settings

　　4. Program List

　　The program first initializes the TMS320VC5410, sets the data page pointer (DP) to 0, and disables interrupts. The TMS320VC5410 is connected to an external 10Hz clock frequency generator, which is multiplied to 100MHz through a phase-locked loop circuit. Then the multi-channel cache serial port McBSP of the TMS320VC5410 is initialized. Finally, data is sent in response to the XRDY interrupt.

　　Conclusion

　　This paper introduces the functional characteristics of the multi-channel buffered serial port (McBSP) of TMS320VC5410, and discusses in detail how to use the SPI interface protocol to achieve communication between McBSP and other serial devices with examples.