TMS320C5402 serial communication synchronous transmission process

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TMS320C5402 serial communication synchronous transmission process [Copy link]

Synchronous transmission
For C5402, synchronization issues are divided into transmission synchronization and reception synchronization. As shown in the hardware system in Figure 12, once the transmission synchronization is valid, the value in the transmission shift register XSP[1,2] is shifted out to the DX pin after the corresponding data delay specified by XDATDLY. Whenever DXR[1,2] is copied to XSR[1,2], the next CLKX falling edge makes XRDY valid, indicating that the next data to be transmitted has been written to the transmission register (DXR[1,2]). When the CPU writes to DXR[1,2], XRDY becomes invalid. Figure 12 is an example of serial transmission.

The period of the frame synchronization signal determines the frame frequency, that is, frame frequency = bit clock frequency / number of bit clocks between frame synchronization signals. The frame frequency can be increased by reducing the time between frame synchronizations. As shown in Figure 13, when the frame transmission frequency increases, the invalid period between adjacent transmitted data packets is reduced to 0. The minimum time between frame synchronizations is the number of bits to be transmitted per frame. The maximum frame frequency is defined as: maximum frame frequency = bit clock frequency / number of bits per frame. By setting the data format output by C5402 McBSP to conform to the data format of the PC RS232 serial port, the problem of data synchronization of C5402 transmission is solved.

Once the receive frame synchronization (FSR) becomes valid, it is detected at the first falling edge of the receiver's CLKR. Then, after the corresponding data delay set by RDATDLY, the data on the DR pin is shifted into the receive shift register (RSR[1,2]). At the rising edge of the clock at the end of each word, the content of RSR[1,2] is copied to RBR[1,2], assuming that RBR[1.2] is not full. Then, a copy of RBR[1,2] to DRR[1,2] sets the RRDY status position to 1 at the next CLKR falling edge. This indicates that the receive data register (DRR[1,2]) is ready for the CPU to read data. When the CPU reads DRR[1,2], RRDY becomes invalid. As shown in Figure 14, serial reception is used. The start bit of the data sent by the RS232 serial port of the PC is always at a low level, and it is used as the frame synchronization signal for the C5402 McBSP to receive data, which solves the synchronization problem of the C5402 receiving data.

In the system, the receiving frame synchronization signal line FSR of C5402 is connected with the data receiving line DR, and the RFIG of the RCR2 register of McBSP is set to 1, that is, the receiving frame synchronization signal after the first word is ignored. In this way, the start of the data sent by the PC asynchronous serial port is used as the receiving frame synchronization signal of C5402 McBSP, and the data after the start bit is prevented from interfering with the frame synchronization signal, thus realizing reliable data transmission between DSP and PC.

The chip used here to convert between COMS logic level and RS232 logic level is MAX232 from MAXIM. Since the supply voltage of MAX232 is 3.3V, two resistors are used in series to divide the voltage to achieve pin voltage matching when receiving data in C5402. From the system hardware connection, it can be seen that this design scheme can realize full-duplex communication between DSP synchronous serial port and PC asynchronous serial port without adding additional hardware. At the same time, it also has the same data transmission rate as general asynchronous serial port and asynchronous serial port.

In the transmission process
, C5402 encodes the data as follows before sending it: first, expand each bit of the data to be sent into 16 bits in order from low to high, such as "0" is expanded into "0000h", "1" is expanded into "FFFFh", so that an 8-character is expanded into 8 16-bit words, and then add a 16-bit data "0000h" in front of this group of data as the end mark. For example, the ASCII of "b" is "0110 0010b", and the encoded group of 10 16-bit data is "0000h, 0000h, FFFFh, 0000h, 0000h, 0000h, FFFFh, FFFFh, 0000h, FFFFh". Set the C5402 McBSP to send data format of 10 words per frame, 16 bits per word, and send each group of 10 data as a frame signal when sending data.

The receiving process of C5402 is the opposite of the sending process. Set McBSP to work in the receiving format of 10 words per frame, 16 bits per word. After C5402 receives a frame of data, it decodes it in the reverse process of the encoding method when sending data to restore the original value.