TMS320C5402 memory, system startup and interrupt, clock (PLL)

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TMS320C5402 memory, system startup and interrupt, clock (PLL) [Copy link]

1. TMS320C5402 Memory The
TMS320C5402 has a total of 192K bytes of addressable memory space. This 192K bytes of memory space is divided into three independent selectable spaces:
(1) 64K bytes of program memory space;
(2) 64K bytes of data memory space;
(3) 64K bytes of I/O space.

The TMS320C5402 chip includes three types of on-chip memories: DARAM, SARAM, and ROM.

All internal and external program memories and internal and external data memories of TMS320C5402 are uniformly addressed.

The memory configuration structure of TMS320C5402 is shown in the figure below

The memory structure of the TMS320C5402 is related to the settings of the processor mode status register (PMST). Users can configure the memory space through three control bits in PMST (MP/MC, OVLY, and DROM).

The program storage space of TMS320C5402 adopts extended paging technology. The entire program storage space (1M bytes/20 address lines) is divided into 16 pages, with each page totaling 64K bytes.

TMS320C5402 has 4K bytes of internal ROM. When MP/MC=0, this 4K bytes of ROM is mapped to the address range of F000H-FFFFH in the program space. The content of the upper 2K bytes of ROM is customized by TI. This 2K bytes of program space (F800H-FFFFH) contains the following content:
(1) Boot program. Automatically load the boot program from the serial port, external memory, I/O port, and host interface.
(2) 256 bytes u-law extension table
(3) 256 bytes A-law extension table
(4) 256 bytes sine function value lookup table
(5) Interrupt vector table
When the processor is reset, the reset, interrupt, and trap vectors are mapped to FF80H in the program space. After reset, these vectors can be remapped to the beginning of any page of the program memory space. Using this feature, it is very convenient to move the interrupt vector table from the boot ROM to other storage areas, and then remove the ROM from the memory map.

2. TMS320C5402 interrupt system
1. Software interrupt and hardware interrupt
C5402 supports both hardware interrupt and software interrupt. Hardware interrupt is divided into external interrupt and internal interrupt. Hardware interrupt from external interrupt port includes six interrupt sources, including RS, NMI, INT0-INT3. The interrupt from on-chip peripherals includes TINT0, TINT1, HPIINT, BRINT0, BXINT0, BRINT1, BXINT1, DMAC0-DMAC6.
Software interrupt is triggered by program instruction, including: INTR, TRAP, RESET.
INTR allows users to execute any interrupt service routine in software. When ISR is executed, the corresponding bit in IFR is cleared and INTM is set to 1. INTR instruction is non-maskable.
The only difference between TRAP instruction and INTR is that TRAP instruction does not affect INTM bit.
RESET instruction generates non-maskable software reset. MP/MC is not sampled during software reset. The initialization of IPTR and on-chip peripherals using RESET instruction reset and hardware reset is different. The RESET instruction is not affected by the INTM bit, but the INTM bit will be set to 1 when the instruction is executed.

2. Non-maskable interrupts and maskable interrupts
Non-maskable interrupts mean that as long as the interrupt signal is generated, the CPU will definitely respond to this interrupt. This type of interrupt includes all software interrupts and two external hardware interrupts: RS and NMI.
Maskable interrupts refer to interrupts that can be masked or enabled by software. Except for RS and NMI, all hardware interrupts are maskable interrupts.

3. Interrupt priority
When multiple hardware interrupts are triggered at the same time, C5402 processes them according to the priority queue. When the priority of an interrupt is 1, it has the highest priority. For C5402, there are 14 fixed interrupt priorities. The interrupt priorities are shown in the following table:
Interrupt number Priority Interrupt name Interrupt address Function0
1 RS/SINTR 0 Reset (hardware/software)
1 2 NMI/SINTR 4 Non-maskable interrupt2
— SINT17 8 Software interrupt #17
3 — SINT18 C Software interrupt #18
4 — SINT19 10 Software interrupt #19
5 — SINT20 14 Software interrupt #20
6 — SINT21 18 Software interrupt #21
7 — INT22 1C Software interrupt #22
8 — SINT23 20 Software interrupt #23
9 — SINT24 24 Software interrupt #24
10 — SINT25 28 Software interrupt #25
11 — SINT26 2C Software interrupt #26
12 — SINT27 30 Software interrupt #27
13 — 8 BXINT0/SINT5 54 Serial port 0 transmit interrupt 22 9 DMAC0/SINT6
58 DMA channel 0 interrupt 23 10 TINT1/DMAC1/SINT7 5C Timer 1 interrupt (default)/DMA channel 1 interrupt 24 11 INT3/SINT8 60 External interrupt 3 25 12 SINT2/SINT4 34 Software interrupt #28 14 — SIN29 38 Software interrupt #29 15 — SIN30 3C Software interrupt
#30 16 3 INT0/SINT0 40 External interrupt 0 17 4 INT1/SINT1 44 External interrupt 1 18 5 INT2/SINT2 48 External interrupt 2 19 6 TINT0/SINT3 4C Timer 0 interrupt 20 7 BRINT0/SINT4 50 Serial port 0 receive interrupt 21 8 BXINT0 / SINT5 54 Serial port 0 transmit interrupt 22 9 DMAC0/SINT6 58 DMA channel 0 interrupt 23 HPINT/SINT9 64 HPI interrupt 26 13 BRINT1/DMAC2/SINT10 68 Serial port 1 receive interrupt (default)/ DMA channel 2 interrupt 27 14 BXINT1/DMAC3/SINT11 6C Serial port 1 send interrupt (default)/ DMA channel 3 interrupt 28 15 DMAC4/SINT12 70 DMA channel 4 interrupt 29 16 DMAC5/SINT13 74 DMA channel 5 interrupt 3031 787F Reserved

4. Interrupt vector table
The interrupt vector table is actually an assembly instruction with a length of 0x0080. Each interrupt in the above table corresponds to an address in the interrupt vector table with a length of 0x0004. The jump instruction is stored in the address space with a length of 0x0004 corresponding to each interrupt, and the destination address of the jump corresponds to the service program (ISR) of the interrupt. When the CPU responds to an interrupt, the program pointer (PC) will jump to the interrupt vector table address corresponding to the interrupt and execute the jump instruction.
The following program is an example of an interrupt vector table. Note: The jump instruction "B pmad" is a double-word instruction, occupying two 16-bit spaces.
.sect ".vectors" ;Define interrupt vector space.ref
_c_int00 ;Define C language program entry interrupt entry address label.ref
_Mcbsp_AD_ISR_tint0 ;Define serial port Mcbsp, A/D conversion, interrupt service routine, timer 0 interrupt entry address label
reset: B _c_int00 ;Hardware reset interrupt, jump directly to program entry address _c_int00
NOP
NOP
nmi: RETE ;Non-maskable interrupt
NOP
NOP
NOP
sint17 .space 4*16 ;Software interrupt
sint18 .space 4*16
sint19 .space 4*16
sint20 .space 4*16
sint21 .space 4*16
sint22 .space 4*16
sint23 .space 4*16
sint24 .space 4*16
sint25 .space 4*16
sint26 .space 4*16
sint27 .space 4*16
sint28 .space 4*16
sint29 .space 4*16
sint30 .space 4*16

int0: RETE ;External interrupt int0
NOP
NOP
NOP
int1: RETE ;External interrupt int1
NOP
NOP
NOP
int2: RETE ;External interrupt int2
NOP
NOP
NOP NOP
tint0: B _Mcbsp_AD_ISR_tint0 ;Timer interrupt 0, jump directly to interrupt address label _Mcbsp_AD_ISR_tint0
NOP
NOP
rint0: RETE ;Serial port 0 receive interrupt
NOP
NOP
NOP
xint0: RETE ;Serial port 0 send interrupt
NOP
NOP
NOP
dmac0: RETE ;Direct memory access channel 0 interrupt
NOP
NOP
NOP
tint1: RETE ;Timer 1 interrupt
NOP
NOP
NOP
int3: RETE ;External interrupt 3
NOP
NOP
NOP
hpint1: RETE ;Host parallel port interrupt
NOP
NOP
NOP
rint1: RETE ;Serial port 1 receive interrupt
NOP
NOP
NOP
xint1: RETE ;Serial port 1 send interrupt
NOP
NOP
NOP
dmac4: RETE ;Direct memory access channel 4 interrupt
NOP
NOP
NOP
dmac5: RETE ;Direct memory access channel 5 interrupt
NOP
NOP
NOP
.end
The interrupt vector address of TMS320C5402 is composed of the 9-bit interrupt vector address pointer IPTR in PMST and the interrupt vector number after 2 bits shifted left. For example: INT0=0001 0000B=10H, 2 bits shifted left becomes 100 0000B=40H, IPTR=0001H, then the interrupt vector address is: 0000 0000 1100 0000H=00C0H. The interrupt vector address is formed as shown in the figure below:

When the hardware is reset, IPTR = 1FFH, so after the hardware is reset, the interrupt vector table address is actually 0FF80H, which cannot be changed. When the software is running, the address of the interrupt vector table can be rearranged by changing the content of IPTR. For example: IPTR = 0001H, the interrupt vector table is moved to the program storage space starting at 0080H. When the experimental system software is simulated, the interrupt vector table is mapped to the program storage space starting at 0080H.

5. Terminal operation process
(1) Receiving interrupt request
When an interrupt request is generated, regardless of whether the CPU responds or not, the corresponding bit in IFR will be set to 1. When the CPU responds to the interrupt, the corresponding flag bit in IFR is automatically cleared (no instruction needs to be executed).
(2) If an interrupt or non-maskable interrupt is entered, the CPU will respond immediately. If it is a maskable hardware interrupt, the following conditions must be met before the CPU will respond.
a. Highest priority
b. INTM = 0. After the CPU responds to the interrupt, INTM is automatically set to 1 (no instruction needs to be executed)
c. The corresponding bit in IMR is 1
(3) After executing the interrupt service program to respond to the interrupt, the CPU will perform the following operations:
a. Push the current value of the program counter PC (return address) onto the stack for storage
b. Load the corresponding address of the interrupt in the interrupt vector table into PC
c. Get the instruction in the interrupt vector table
d. Execute the instruction in the interrupt vector table. The jump instruction makes the program point to the interrupt service routine (ISR)
e. Execute the interrupt service routine (ISR) until it returns
f. Take the return address from the stack and load it into PC
g. Continue to execute the main program

6. Interrupt Service Routine (ISR)
When writing an interrupt service routine, you need to pay attention to the following: protect the scene at the beginning of the program, and save the registers or variables to be changed in the interrupt service routine on the stack; restore the scene at the end of the program and restore the original values of the registers or variables. When the program returns from the ISR, it is recommended to use the RETE instruction. When writing an interrupt service routine in C language, use interrupt to define the interrupt service routine, so that the compiler will automatically generate code to protect and restore the scene.
The following is a code for an interrupt service routine:
_KEY:
PSHM ST0; protect the scene
PSHM ST1
PSHM AH
PSHM AG

Execute interrupt service

POPM AG ;Restore the scene
POPM AL
POPM AH
POPM ST1
POPM ST0
RETE ;Return

3. Clock (PLL)
The input clock of TMS320C5402 is input to 5402 after being divided by two, or after being multiplied by the PLL circuit. The reset state uses the input clock divided by two mode. When the PLL is set, the clock after setting the PLL continues to run.
The software programmable phase-locked loop can work in two modes:
PLL mode: The input clock pin (X2/CLKIN pin) is multiplied by a possible ratio of 1 to 31, which requires the use of the PLL circuit;
DIV (divider) mode: The clock of the input pin is divided by 2 or 4. This mode can completely disable the PLL circuit to reduce power.
The software programmable phase-locked loop is controlled using the 16-bit memory-mapped (address 0058h) clock mode register (CLKMD). The CLKMD register is used to define the configuration of the phase-locked loop clock module. After reset, the clkmd register is initialized to a predetermined value depending only on the state of the CLKMD1CLKMD3 pins as shown in the following table: