Effects of Clock Jitter and Phase Noise on Sampling Systems

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Effects of Clock Jitter and Phase Noise on Sampling Systems [Copy link]

As higher resolution data converters with direct IF sampling become available, system designers must make decisions about low jitter clock circuits that help balance performance and cost. Many of the traditional methods used by manufacturers to specify clock jitter do not apply to data converters, or, at best, only reflect part of the problem. Without a proper understanding of the specification and design of the clock circuit, you cannot achieve the best performance from these data converters.