Three-phase Vienna topology technology detailed introduction

alan000345 · Published on 2018-12-27 09:37

Three-phase Vienna topology technology detailed introduction [Copy link]

Charging modules have been popular in recent years, with power levels increasing from 7.5 kW and 10 kW at the beginning to 15 kW and 20 kW later. Most of the high-power charging modules on the market now have three-phase input, and the PFC part basically adopts the three-phase Vienna structure topology without neutral line.

Composition of the main circuit

1. Main topology

As shown in Figure 1, the main topology is the main circuit of the three-phase Vienna PFC topology:

[font=Arail, 1) Three-phase diode rectifier bridge, using ultra-fast recovery diodes or SiC diodes;

2) Each phase has a bidirectional switch, and each bidirectional switch is composed of two MOS tubes. It utilizes its inherent anti-parallel body diode and shares the driving signal, which reduces the difficulty of control and driving. Compared with other combination schemes, it has the advantages of high efficiency and small number of devices;

3) The number of semiconductors through which the current flows is the least: Taking phase a as an example, when the bidirectional switch Sa is turned on, the current flows through two semiconductor devices, euo = 0, and the midpoint of the bridge arm is embedded in the midpoint of the PFC bus capacitor; when the bidirectional switch is turned off, the current flows through a diode, when iu > 0, euo = 400V, when iu < 0, euo = -400V, and the midpoint of the bridge arm is embedded in the PFC positive bus or negative bus.

[font=Arail, The working mode of the circuit relies on controlling the on and off of Sa, Sb, and Sc to control the charging and discharging of the PFC inductor. Since the PF value of PFC is close to 1, when analyzing its working principle, it can be assumed that the inductor current and the input voltage are in phase, the three-phase electricity is balanced, and the phase difference is 120 degrees. 2. Equivalent Circuit1) The three-phase three-level Boost rectifier can be considered as three single-phase voltage-doubler Boost rectifiers in Y-type parallel connection;2) Three high-frequency Boost inductors use CCM mode to reduce switching current stress and EMI noise;3) Two electrolytic capacitors form the midpoint of the capacitor, providing the conditions for three-level operation;

Figure 3 Single-phase rectifier circuit

Figure 4 Equivalent circuit of the main circuit

According to the equivalent circuit, the expressions of each parameter are as follows:

Note:The expression of eun is very important and is the basis for many subsequent formula calculations. It is derived as follows.

Equivalent to the main circuit shown in Figure 1:

Figure 5 Circuit equivalent diagram

List the balanced equations of the circuit, where the three-phase balance is:

At any time:

Simplified to get:

[color =#222222]Therefore:

Where Vuo, Vvo, Vwo are the voltages at the three-phase terminals A, B and C, L ＝ La= Lb= Lc.

III. Working principle

1. Switching state of the main circuit

The three-phase AC voltage waveform is shown in Figure 6. The phase difference between UV and W is 120 degrees.

Figure 6 Three-phase AC voltage waveform

It can be seen from the main circuit that when the switches Sa, Sb, and Sc of each phase are turned on, U, V, and W are connected to the midpoint O of the capacitor, and the inductors La, Lb, and Lc are charged through Sa, Sb, and Sc. When the switches of each phase are turned off, U, V, and W are connected to the positive level (when the current is positive) or the negative level (when the current is negative) of the capacitor, and the inductor is discharged through D1-D6. Taking 0~30 degrees as an example, ia and ic are greater than zero, and ib is less than zero.

Each bridge arm midpoint has three states, three bridge arms means 3^3=27 states, but it cannot be PPP and NNN at the same time, so there are 25 switch states in total; see the attachment for switch states!

1539055537231750.xlsx (38.52 KB, downloads: 36)

2. Main circuit wave generation mode

The working state of the main circuit is closely related to the wave generation scheme. Different wave generation schemes will produce different working states in each cycle. Generally, Vienna topology adopts DSP digital control, which is flexible and portable.

(1) Using a single-channel sawtooth carrier modulation The modulation signal output by the current loop controller is fed to the sawtooth carrier, as shown in Figure 7, to maintain a constant switching frequency; in the 0~30 degree sector, 4 switching states are generated in each cycle. Due to the asymmetry of the waveform, the harmonics of the switching ripple of the current waveform are relatively large; using this method for debugging, the maximum step of the bridge arm midpoint line voltage is 2Ed (Ed is half of the bus voltage, 400V);

Figure 7 Sawtooth wave carrier method

[font=Arail, (2) A high-frequency triangular carrier with a phase difference of 180 degrees is used, as shown in Figure 8. When the corresponding input voltage is in the positive half cycle, Trg1 is used, and when the corresponding input voltage is in the negative half cycle, Trg2 is used. Eight switching states are generated in each cycle. Compared with the traditional control scheme that generates four switching states, the eight switching states are equivalent to doubling the frequency, which reduces the ripple of the input current and is beneficial to the THD index;

Figure 8 Triangular wave carrier mode

The simulation waveform of the triangular wave carrier mode is shown in Figure 9:

Figure 9 Triangular wave carrier mode simulation waveform

(2) A high-frequency triangular carrier with a phase difference of 180 degrees is used, as shown in FIG8. When the corresponding input voltage is in the positive half cycle, Trg1 is used, and when the corresponding input voltage is in the negative half cycle, Trg2 is used. Eight switching states are generated in each cycle. Compared with the traditional control scheme that generates four switching states, eight switching states are equivalent to doubling the frequency, which reduces the ripple of the input current and is beneficial to the THD index. "]

Figure 8 Triangle wave carrier method

The simulation waveform of the triangle wave carrier method is shown in Figure 9:

Figure 9 Triangle wave carrier simulation waveform

(2) A high-frequency triangular carrier with a phase difference of 180 degrees is used, as shown in FIG8. When the corresponding input voltage is in the positive half cycle, Trg1 is used, and when the corresponding input voltage is in the negative half cycle, Trg2 is used. Eight switching states are generated in each cycle. Compared with the traditional control scheme that generates four switching states, eight switching states are equivalent to doubling the frequency, which reduces the ripple of the input current and is beneficial to the THD index. "]

Figure 8 Triangle wave carrier method

The simulation waveform of the triangle wave carrier method is shown in Figure 9:

Figure 9 Triangle wave carrier simulation waveform

电容器 · Published on 2018-12-27 09:44

This three-phase Vienna is quite complicated.

alan000345 · Published on 2018-12-28 09:01

Capacitors published on 2018-12-27 09:44 This three-phase Vienna is quite complicated.

It is indeed complicated, and there is more information. I will continue to share it today.

alan000345 · Published on 2018-12-28 09:04

3. Working Status

As mentioned above, the three-phase three-level PFC can be regarded as three single-phase PFCs. Each single phase is equivalent to two Boost circuits, which work alternately in the positive and negative half cycles of the AC voltage. The positive half cycle is as follows:

Figure 10 Single-phase ON-OFF current waveform

Take phase a as an example. When the drive signal is high, the switch tube Q1 is turned on (positive half cycle of AC voltage) or Q2 is turned on (negative half cycle of AC voltage); when the drive signal is low, both switch tubes Q1 and Q2 are turned off. In the positive half cycle of voltage, the upper bridge arm diode of phase a is turned on; in the negative half cycle of voltage, the lower bridge arm diode of phase a is turned on.

Through the above analysis, a triangular carrier with a phase shift of 180 degrees is used for modulation. In the sector of 0~30 degrees, there are 8 switching states and 4 working modes: ONO, ONP, OOP, and POP.

ONO working mode: phase a and phase c are turned on, phase b is turned off, voltages of U and W are 0, voltage of point V is -400V; in this working state, only C2 is charged;

Figure 11 ONO switch status

ONP working mode: phase a is turned on, phase b and phase c are turned off; the voltage at point U is 0, the voltage at point V is -400V, and the voltage at point W is +400V;

Figure 12 ONP switch status

OOP working mode: U and V point voltage is 0, W point voltage is +400V;

Figure 13 OOP switch status

[p=null, 2, POP working mode: the voltage of points U and W is +400V, the voltage of point V is 0, this working mode only charges C1;

Figure 14 POP switch status

Of course, this is only the working state in the 0~30 degree sector. In fact, there are 25 working states in the entire power frequency cycle. For details, please see the switch state attachment I sent above. The state of charging C1 or C2 in the two working modes of ONO and POP only plays a decisive role in the subsequent bus voltage equalization.

There is also an analysis and introduction of related device stress, which will be shared tomorrow. I will share the formulas and principles bit by bit, otherwise I can't read it.

alan000345 · Published on 2018-12-29 11:21

IV. Analysis of device stress

1. PFC inductor stress

From the above working state, we can know that the front end of the PFC inductor is connected to the input, and the rear end voltage is connected to the three potentials of the PFC capacitor in different switch states, P, O, N. We take the midpoint of the three-phase input as the reference, the PFC bus voltage is fluctuating, and the voltages in the three states are:

Where Vu, Vv, Vw are the voltages of the three-phase switch endpoints relative to the midpoint of the bus capacitor. Taking phase A as an example, when Va>0, Vu can be 0, 400V, and the remaining B and C phases can be any vector except (400V, 400V). Because phases B and C cannot be positive at the same time, the voltage range of the right end of the PFC inductor is -266~533V.

[font=Arail, Similarly, when Va<0, Vu can be 0, -400V, and the other B and C phases can be any vector except (-400V, -400V), so the voltage range of the right end of the PFC inductor is -533～266V. The voltage peak across the inductor appears when the phase is 60 degrees (after 60 degrees, the other two phases are negative, and the maximum voltage from GND to O becomes 133V. Therefore, the peak voltage drop can be seen from the simulation. The maximum value is:

2. MOSFET and diode stress

As shown in Figure 1, the two diodes of each phase are connected across the positive and negative busbars, and the level of the midpoint can be 0, -400V, 400V. Therefore, for the diode, the maximum platform voltage at both ends is the output PFC output voltage. Considering the voltage spike caused by the MOS switch for the 800V busbar voltage, the maximum spike voltage of the diode will be close to 1000V, and its current stress can be calculated by the control equation.

In fact, when considering the rectifier diode, not only the withstand voltage and current carrying capacity should be considered, but also the ability to resist surge impact is a very important parameter. In the actual debugging process, there is an attempt to use SiC diodes, but the ability of SiC diodes to resist surge impact current is relatively weak, so generally ultra-fast recovery high-voltage diodes are used, such as Microsemi's ATP30DQ1200B series.

We know that when the module is in surge, the current will take the low-impedance path. Generally, the varistor of the front stage will discharge part of the current, but the varistor will not discharge all the current, and a large amount of current will still remain in the subsequent current. For single-phase modules, the general practice is to add a diode to the PFC bus capacitor in front of the PFC inductor. In this way, the surge current will be introduced into the PFC bus capacitor through the lightning protection diode to protect the power device. However, for three-phase PFC, the PFC capacitor is a five-level fluctuation, and this method cannot be used. Otherwise, when the circuit is working normally, current will flow through the diode and cause Vienna to fail to work. Therefore, a large current will enter the bus capacitor through the inductor and PFC Diode. At this time, the PFC Diode is required to have a strong ability to resist surge current.

The VDS voltage of MOSFET, due to the use of three-level technology, makes the MOSFET voltage only half of the 800V bus voltage of the three-phase PFC. Considering the peak, this voltage will be close to 600V. For MOS voltage stress, we are most concerned about the potential difference between the midpoint of the top MOS and the reference ground of the three-phase input. If an isolated optocoupler is used for driving, this voltage determines the selection of the isolated drive optocoupler.

V. Control Scheme

We know that this control circuit generally adopts a dual-loop control method, that is, voltage outer loop + current inner loop. The voltage outer loop obtains a stable output DC voltage for use by the subsequent circuit (such as Three Level LLC, PS Interleave LLC, PSFB, etc.), and the current inner loop obtains a nearly sinusoidal input current to meet the requirements of THD and PF values.

Figure 15 Control loop

[p=null, 2,In fact, digital control is nothing more than converting analog solutions into digital operations. You can refer to the analog PFC control logic block diagram shown in Figure 16 and use its control concept to achieve digitization.

Figure 16 Analog control block diagram

[p=null, 2, The PFC bus output voltage is sampled and filtered by the DSP's ADC and then sampled into the DSP. It is compared with the voltage given signal, and after the error is generated, an A signal is output after the Gvc(s) compensation. Then, it is multiplied by the AC voltage through a multiplier to obtain the current given signal. It is the role of the multiplier that ensures that the input voltage and current are in phase, so that the PF value at the input end of the power supply is close to 1. The sampled inductor current waveform is compared with the current given to obtain the error. After the Gic(s) compensator is used for compensation, the output value of the current loop is obtained. This value is directly modulated with the carrier to obtain a PWM waveform to control the voltage and current. The general control block diagram can be simplified as shown in the following figure, as shown in Figure 17;

Figure 17 PFC transfer function block diagram

Where: Gcv(s) is the compensation function of the voltage loop, Gci(s) is the compensation function of the current loop, Hi(s) is the current loop sampling function, Hv(s) is the voltage loop sampling function, Gigd(s) is the function of the inductor current to the duty cycle D.

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VI. Choice of control ground

In traditional single-phase bridge PFC, the negative electrode of the PFC capacitor is generally used as the control AGND, because the voltage at this point is connected to the input L and N through the rectifier bridge. When the input is in the positive half cycle, AGND is clamped to the N line by the rectifier bridge; when the input is in the negative half cycle, AGND is clamped to the L line by the rectifier bridge; therefore, the negative electrode of the bus capacitor AGND (equivalent to PE) is a change of industrial frequency. Since the input is generally 50Hz AC, it is relatively stable and can be used as the control ground of the control circuit.

However, compared with Vienna PFC, it is different. The midpoint of the bus capacitor relative to the midpoint of the power frequency voltage (PE) is a 5-level high-frequency change level at the switching level: ±2/3Vo, 0, ±1/3Vo (Vo here represents half of the bus voltage, with a typical value of 400V. Please refer to the eon in the switch state attachment for how the 5 levels are generated). If such a large high-frequency fluctuation is used as the control ground, then the noise and common-mode interference will be very large, which may cause inaccurate sampling voltage and drive, seriously affecting the reliability of the circuit.

Since the high-frequency change of the midpoint of the capacitor cannot be used as the control ground, what should we do? Can we construct a virtual ground as the control ground AGND? We can use the Y-type connection method to generate a virtual ground as the control ground by connecting the three-phase input through a voltage divider resistor. However, after constructing this control ground, all other sampling and driving must work in a differential and isolated manner relative to this control ground. In this way, the midpoint O of the output capacitor is separated from the control ground AGND, avoiding interference caused by high-frequency drastic changes.

Figure 18 Control area AGND

Does this perfectly solve the control ground problem? In the actual working process, AGND still has violent fluctuations. It is not as calm as we imagined. AGND fluctuates violently along with O, and the peak-to-peak value of AGND is very large.

How to solve it? The fundamental reason is that there is a sampling resistor connection between AGND and O (sampling of output voltage), and there is a Y capacitor connection between AGND and PE. Under the action of the high-frequency signal at point O, AGND is naturally forced to share a certain proportion of the voltage. The solution is to add a low-resistance path between AGND and PE to reduce the impedance and bear a certain voltage to reduce the ripple voltage of AGND-PE.

VII. Analysis of bus voltage equalization principle

We know that the bus voltage 800V of the three-phase Vienna PFC topology is divided by two capacitors C1 and C2 in series. The potential O at the midpoint of the capacitor is determined by the charging and discharging of the capacitor. The voltages of the two capacitors should be balanced to maintain the true three-level operating conditions. Otherwise, the output voltage may contain undesirable harmonics and even affect the integrity of the circuit. The balance of the positive and negative busbars of the three-phase three-level PFC will affect the performance of the PFC: 1. Input current THD; 2. The stress of the power switch tube and diode (their own and the subsequent power circuit); 3. The busbar capacitor is prone to overvoltage during dynamic operation;

The potential deviation of the capacitor midpoint is related to the charging and discharging process of the positive and negative busbar capacitors of the PFC. It can be seen from the attached switch state that there is no current flowing into or out of the capacitor midpoint in the working state of group a and group z, so the charging and discharging of the two capacitors are the same and no bias is generated. Only the switching state of groups b, c, and d will affect the difference in the charging and discharging of the PFC busbar capacitor and generate bias.

According to the previous working principle analysis, the POP working state only charges the capacitor C1, and the ONO working state only charges the capacitor C2. Therefore, the midpoint potential can be controlled according to these two working states. In the control, the action time of the two working states of ONO and POP can be adjusted to balance the voltage.

Figure 19 C2 charging

Figure 20 C1 charging

At this time, a bias loop can be added to the entire control loop to adjust the action time of ONO and POP to balance the bus voltage.

Specific implementation method: the positive bus and the negative bus are sampled respectively, and then the difference (DC component) is obtained. The difference is adjusted by the compensator of the bias loop and superimposed on the input current reference sine wave. After precise rectification, it is transformed into a double half-wave with different amplitudes as the given current loop, so as to change the action time of ONO and POP and improve the PFC bus voltage balance.

Figure 21 Bias setting

As shown in Figure 22, compa, compb and compc are the results calculated by the current loop of each phase. Taking the 0~30 degree sector as an example, when the voltage of the positive bus relative to the midpoint is lower than that of the negative bus, the setting of the positive half-wave becomes smaller, the setting of the negative half-wave becomes larger, the time of the POP working state becomes longer, and the charging time for the positive bus capacitor becomes longer; the time of the ONO working state becomes shorter, and the charging time for the negative bus capacitor becomes shorter. When the voltage of the positive bus relative to the midpoint is higher than that of the negative bus, the given value of the positive half-wave becomes larger, the given value of the negative half-wave becomes smaller, the action time of POP becomes longer, the time for charging the positive bus capacitor becomes shorter, the action time of ONO becomes longer, and the charging time for the negative bus becomes longer. In the figure, the solid line of comp value represents the value of the previous cycle, and the dotted line represents the value of the current cycle; the shaded part represents the time of change;

Figure 22 Schematic diagram of voltage balance control

The above description is that when the main power circuit is working normally, the voltage of the PFC bus capacitor can be controlled by adjustment, but what about when the module is started? The auxiliary power supply can be used to directly draw power from +400V~-400V. Due to the difference in capacitors, the internal resistance cannot be completely equal, and the bias voltage will also be generated. Another thing is to use a higher-level MOSFET, which is costly. In addition, the standby loss of the charging module is also a problem. Many customers require that the standby loss of the module cannot exceed a certain amount.

Of course, there is another way to draw power from the auxiliary power supply, which is also the mainstream way of manufacturers now. That is, an auxiliary power supply is hung on both the positive and negative busbars. When starting the machine, the bus capacitor is charged through the charging resistor. The transformer adopts the winding competition method. Whoever has a higher bus voltage will be used to supply power. This can well ensure the voltage balancing effect of the module during the starting process; after the module works normally, the same principle applies. However, drawing power directly from +800V does not have this effect.

Figure 23 Schematic diagram of auxiliary power supply

There is more content to share. I hope everyone will pay attention. This three-phase Vinenna topology technology does require a lot of knowledge.

png[/img]

Figure 21 Bias setting

As shown in Figure 22, compa, compb and compc are the results calculated by the current loop of each phase. Taking the 0~30 degree sector as an example, when the voltage of the positive bus relative to the midpoint is lower than that of the negative bus, the given value of the positive half-wave becomes smaller, the given value of the negative half-wave becomes larger, the time of the POP working state becomes longer, and the charging time for the positive bus capacitor becomes longer; the time of the ONO working state becomes shorter, and the charging time for the negative bus capacitor becomes shorter. When the voltage of the positive bus relative to the midpoint is higher than that of the negative bus, the given value of the positive half-wave becomes larger, the given value of the negative half-wave becomes smaller, the action time of POP becomes longer, the time for charging the positive bus capacitor becomes shorter, the action time of ONO becomes longer, and the charging time for the negative bus becomes longer. In the figure, the solid line of comp value represents the value of the previous cycle, and the dotted line represents the value of the current cycle; the shaded part represents the time of change;

Figure 22 Schematic diagram of voltage balance control

The above description is that when the main power circuit is working normally, the voltage of the PFC bus capacitor can be controlled by adjustment, but what about when the module is started? The auxiliary power supply can be used to directly draw power from +400V~-400V. Due to the difference in capacitors, the internal resistance cannot be completely equal, and the bias voltage will also be generated. Another thing is to use a higher-level MOSFET, which is costly. In addition, the standby loss of the charging module is also a problem. Many customers require that the standby loss of the module cannot exceed a certain amount.

Of course, there is another way to draw power from the auxiliary power supply, which is also the mainstream way of manufacturers now. That is, an auxiliary power supply is hung on both the positive and negative busbars. When starting the machine, the bus capacitor is charged through the charging resistor. The transformer adopts the winding competition method. Whoever has a higher bus voltage will be used to supply power. This can well ensure the voltage balancing effect of the module during the starting process; after the module works normally, the same principle applies. However, drawing power directly from +800V does not have this effect.

Figure 23 Schematic diagram of auxiliary power supply

There is more content to share. I hope everyone will pay attention. This three-phase Vinenna topology technology does require a lot of knowledge.

png[/img]

Figure 21 Bias setting

As shown in Figure 22, compa, compb and compc are the results calculated by the current loop of each phase. Taking the 0~30 degree sector as an example, when the voltage of the positive bus relative to the midpoint is lower than that of the negative bus, the given value of the positive half-wave becomes smaller, the given value of the negative half-wave becomes larger, the time of the POP working state becomes longer, and the charging time for the positive bus capacitor becomes longer; the time of the ONO working state becomes shorter, and the charging time for the negative bus capacitor becomes shorter. When the voltage of the positive bus relative to the midpoint is higher than that of the negative bus, the given value of the positive half-wave becomes larger, the given value of the negative half-wave becomes smaller, the action time of POP becomes longer, the time for charging the positive bus capacitor becomes shorter, the action time of ONO becomes longer, and the charging time for the negative bus becomes longer. In the figure, the solid line of comp value represents the value of the previous cycle, and the dotted line represents the value of the current cycle; the shaded part represents the time of change;

Figure 22 Schematic diagram of voltage balance control

The above description is that when the main power circuit is working normally, the voltage of the PFC bus capacitor can be controlled by adjustment, but what about when the module is started? The auxiliary power supply can be used to directly draw power from +400V~-400V. Due to the difference in capacitors, the internal resistance cannot be completely equal, and the bias voltage will also be generated. Another thing is to use a higher-level MOSFET, which is costly. In addition, the standby loss of the charging module is also a problem. Many customers require that the standby loss of the module cannot exceed a certain amount.

Of course, there is another way to draw power from the auxiliary power supply, which is also the mainstream way of manufacturers now. That is, an auxiliary power supply is hung on both the positive and negative busbars. When starting the machine, the bus capacitor is charged through the charging resistor. The transformer adopts the winding competition method. Whoever has a higher bus voltage will be used to supply power. This can well ensure the voltage balancing effect of the module during the starting process; after the module works normally, the same principle applies. However, drawing power directly from +800V does not have this effect.

Figure 23 Schematic diagram of auxiliary power supply

There is more content to share. I hope everyone will pay attention. This three-phase Vinenna topology technology does require a lot of knowledge.

"]Of course, there is another way to get power from the auxiliary power supply, which is also the mainstream method of manufacturers now. That is, an auxiliary power supply is hung on the positive and negative busbars. When starting the machine, the busbar capacitor is charged through the charging resistor. The transformer adopts the winding competition method. Whoever has a higher busbar voltage will be used to supply power. This can well ensure the voltage equalization effect of the module during the starting process; after the module works normally, the same principle applies. Directly taking power from +800V does not have this effect.

Figure 23 Auxiliary power supply schematic diagram

There is more content to share. I hope everyone will pay attention to it. This three-phase Vinenna topology technology does require a lot of knowledge.

"]Of course, there is another way to get power from the auxiliary power supply, which is also the mainstream method of manufacturers now. That is, an auxiliary power supply is hung on the positive and negative busbars. When starting the machine, the busbar capacitor is charged through the charging resistor. The transformer adopts the winding competition method. Whoever has a higher busbar voltage will be used to supply power. This can well ensure the voltage equalization effect of the module during the starting process; after the module works normally, the same principle applies. Directly taking power from +800V does not have this effect.

Figure 23 Auxiliary power supply schematic diagram

There is more content to share. I hope everyone will pay attention to it. This three-phase Vinenna topology technology does require a lot of knowledge.

alan000345

VIII. Principle Simulation

1. Input Current

Input current waveform. The parameters are not adjusted properly. Please bear with it.

[font=Arail, 2. Voltage waveforms at each point

The ratio of the input line voltage peak value to the PFC total bus voltage is defined as the modulation coefficient m, m=Vlp/2Ed; where Vlp is the peak value of the line voltage; the rectifier can be considered as a voltage source connected to the AC power through the PFC inductor. In order to make the input current sinusoidal, the bridge arm midpoint line voltage should also be a sinusoidal waveform. In actual situations, the bridge arm midpoint line voltage is a sinusoidal PWM waveform, and harmonic components and maximum step are two main considerations.

(1) When the input line voltage peak value is greater than Ed, the bridge arm midpoint line voltage voltage waveform euv is a 5-step voltage waveform with an amplitude of 0, ±400V, ±800V, and a step of 400V;

[p=null, 2, (2) When the peak value of the input line voltage is less than Ed, the bridge arm midpoint line voltage waveform is a 3-step voltage waveform with an amplitude of 0, ±400V and a step of 400V;

Figure 26 Bridge arm midpoint voltage 2

The voltage waveform eun at the midpoint of the bridge arm relative to the midpoint of the AC power supply is a 9-step voltage waveform; the amplitude is 0, ±133V, ±266V, ±400V, the minimum step is 133V, and the maximum step is 266V; due to the parasitic capacitance between the power switch tube and the heat sink, this step signal will generate common mode noise;

Figure 27 eun voltage waveform

The voltage waveform eon at the midpoint O of the capacitor relative to the midpoint of the AC power supply is a 5-step waveform with an amplitude of 0, ±133V, ±266V, and a step of 133V;

Figure 28 eon voltage waveform 1

Figure 29 eon voltage waveform 2

Figure 30 eon voltage waveform 3

Finally, attach a circuit startup waveform:

[font =Arail, "]Figure 31 Startup waveform

电容器

Thanks for sharing, the content is really comprehensive.

alan000345

The input AC voltage and inductor current, as well as the PFC bus voltage are sampled and filtered by the ADC port of the DSP and sampled into the DSP. Then, they pass through a voltage feedback compensator Gcv (S) to output the feedback signal Vc of the voltage loop. Then, a multiplier unit is used to multiply the output Vc of the voltage regulator with the full-wave rectified waveform of the input voltage to obtain the command value Iref of the current after the rectifier bridge. It is this multiplier that ensures that the input current and input voltage are in phase and have the same waveform, so that the power factor at the power input end is 1. It is the key to realizing the power factor correction function. In the circuit shown in Figure 1, the PFC reference current synthesizer also includes a square circuit and a divider for the full-wave rectified value of the input voltage, mainly to improve the dynamic response speed of the control system to input voltage changes. It is more necessary for applications with a wide input voltage range and large input voltage fluctuations. We represent the above circuit block diagram with a transfer function block diagram: PFC transfer function block diagram

Where: Gcv(s) is the compensation function of the voltage loop, Gci(s) is the compensation function of the current loop, Vm is the carrier amplitude, Gigd(s) is the function of the inductor current to the duty cycle D, ZL(s) is the impedance from the inductor current to the output voltage, Hi(s) is the current loop sampling function, and Hv(s) is the voltage loop sampling function.

2. PFC current loop

[color=rgb(34, 34,back 34)]

[fontbackcolor=transparent][ =&]Figure 34 PFC current loop block diagram

In the Vienna circuit, the two groups of PFC bus capacitors are equivalent to two parallel capacitor groups based on the midpoint as the reference to the input, and the three-phase diode current charges them. For the output, they are equivalent to two series capacitors, supplying power to the load, so the relationship between the current flowing into the PFC capacitor and the current flowing out of the PFC capacitor in each phase is 2/3. Therefore, the main circuit transfer function of the three-phase Vienna topology is:

34)]L_fulload is the PFC inductance value under full load, and RL is the inductor series resistance.

After we know the transfer function of the main circuit, other transfer functions such as AD gain (including sampling, holding, conversion), hardware sampling circuit, Fm, etc. can be expressed. In this way, the open-loop transfer function except the compensator is clear, and the Bode diagram except the compensator is calculated or simulated. According to the Bode diagram of the open-loop transfer function, a reasonable compensator can be designed. In digital power control, the commonly used compensators include PI controller, SZSP controller, 2P2Z controller, 3P3Z controller, etc. Below the switching frequency, the current loop open-loop transfer function is a single-pole system, and the compensation function can be designed as a PI control system.34)]Since the inductance of the PFC inductor changes significantly under different DC biases, the nFeSi material differs by nearly 3 times between the zero point and the peak of the sinusoidal current. In order to improve the low-frequency gain and bandwidth of the zero point while ensuring stability near the peak, we need to adjust the relevant parameters of the current loop in real time, so that the bandwidth and gain can be improved from time to time.

3. Voltage ring

[color=rgb(34, 34,backcolor 34)][ font=&]

[color=rgb(34, 34,backcolor 34)]Figure 35 PFC voltage loop

The PFC current inner loop and the power stage form a current source, so the controlled object of the PFC voltage loop can be equivalent to a current source driving the capacitor at low frequency. At a frequency of around 100Hz, the voltage loop open-loop transfer function is a single-product system. While ensuring that the output voltage is stable when the load changes, the bandwidth of the PFC voltage loop should be low enough so that the loop gain is low enough when the frequency is greater than 100Hz to reduce the modulation effect of the 100Hz voltage ripple on the PFC output capacitor on the PFC input current. Otherwise, the modulation effect will cause serious distortion of the input current. Of course, too low a voltage loop bandwidth will result in too slow a voltage dynamic speed. If the THD design meets the requirements, the bandwidth can be adjusted.

The above is a design for a steady-state voltage loop. If the input or output is dynamically changing, a fast loop can be added to ensure the reliability of the circuit. That is, in dynamic conditions, in order to speed up the loop response and meet dynamic requirements, another set of loop parameters is used, and software filtering is removed at the same time. When the total bus voltage sampling is greater than or less than a certain value given by the current total bus voltage, the fast loop is entered; when the total bus voltage sampling is no longer greater than or less than another value given by the current total bus voltage, the fast loop is exited. Of course, since the ESR of the bus capacitor is easily affected by the ambient temperature, when the ambient temperature is too low, the ESR of the bus capacitor increases, and the voltage loop is adjusted too quickly, which will cause the bus voltage to be overvoltage. Therefore, the design of the voltage loop must not only take into account the low bandwidth of the steady state, but also the dynamic response and the influence of ambient temperature. 4. Bus voltage bias ring The PFC circuit has positive and negative bus outputs, so it is necessary to control the balance of positive and negative outputs: . Superimpose it on the voltage waveform given, so that the bus balance can be adjusted (see the analysis of the voltage balancing principle).

The bus voltage bias loop is a pure proportional link, that is, there is static error regulation, so even if the final regulation is stable, there will still be a certain difference in the bus. If K is larger, the δ output will be larger, the regulation ability will be stronger, and the balance will be better, but the harmonics injected into the input current will also be larger, affecting the THD index. Therefore, a balance needs to be made between THD and bus balance.

In order to eliminate the static difference between the positive and negative busbars, the PI link can be used to replace the pure proportional link, but the integral link itself has the problem of desaturation. For the system with constantly changing Vp and Vn, the voltage regulation is to change the duration of the small vector. The integral response speed is slow, which may over- or under-regulate the small vector, causing the positive and negative busbar voltages to be in a biased state. Therefore, the use of a pure proportional link to regulate the positive and negative busbar voltages can ensure timeliness. Since the adjustment of the bus bias loop will affect THD, the proportional coefficient and the maximum range of output δ should be selected according to the bus bias program to avoid excessive adjustment. 5. Digitalization of compensator The design process of digital compensator is as follows:34)]1) First select a suitable known prototype filter transfer function (select appropriate zeros and poles);

2) Map the s-domain transfer function of the prototype filter to the z-domain;

3) Convert the z-domain into a linear difference equation in the time domain;

For the transformation from s domain to z domain, we generally use bilinear transformation, also known as Tustin transformation and trapezoidal transformation. It converts the analog transfer function in s domain into the equivalent digital transfer function in z domain. It is only an approximation of the representation. The lower the crossover frequency relative to the sampling frequency, the more reliable the approximation. Taking the design of 3P3Z controller as an example, the expression in the s domain is:

34)]Perform a bilinear transformation and bring Hc(s) into Hc(s). After simplification, we can get the z-domain expression:

34)]Convert the z-domain into a linear difference equation:

The general process executed in the MCU is shown in Figure 36:

34)]