My opinion on blocking and non-blocking assignments in FPGA Verilog language

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My opinion on blocking and non-blocking assignments in FPGA Verilog language [Copy link]

For Verilog beginners, blocking assignment and non-blocking assignment should be distinguished. I guess the common explanation of the application of these two assignment methods, when to use blocking assignment and when to use non-blocking assignment, is that non-blocking assignment is usually used in sequential logic and blocking assignment is usually used in combinational logic. However, this is necessarily ambiguous, and it does not mean that blocking assignment is not allowed in sequential logic and non-blocking assignment is not allowed in combinational logic. So I think it is necessary to clarify the subtle difference between blocking assignment and non-blocking assignment. First of all, let's go back to the definition. The so-called blocking assignment, for example, a=b; when this assignment statement is executed, no other statements are allowed to be executed, which is the reason for blocking. And non-blocking assignment, for example, a<=b; when this assignment statement is executed, it does not hinder the execution of other statements. For FPGA, compared with microcontrollers (even high-speed microcontrollers), its own advantage is the parallelism of statement execution, while microcontroller statement execution is sequential. So if we want to make full use of the advantages of FPGA, then we should try to use non-blocking assignment. Below I would like to analyze the difference between the two from a simple example. This is a simple frequency division program, the purpose is to divide the clk clock by four. The initial value of count is 0, (personal experience, because it seems that there is no way to initialize variables in Verilog), then when the rising edge of the first clock arrives, count is incremented by 1 and becomes 1, the if statement is executed as false, and then when the rising edge of the second clock arrives, count is incremented by 1 and becomes 2, the if statement execution condition is true, then the content in the if statement is executed, the data_a data is flipped, and count is reassigned to 0, so the program is that the data_a data is flipped once every two clock rising edges, and the effect of four-frequency division is obtained. The figure below is the simulation waveform, which is completely worthy of analysis. The above program uses blocking assignment, that is, when count is incremented by 1, no other statements can be executed. Therefore, this is a bit like the C language in the microcontroller, an always block that is executed sequentially. What will happen if all the assignments in the above program are changed to non-blocking assignments? First, let's compare the simulation waveforms without analyzing them. From the simulation waveform, this program has indeed become a six-frequency division of the clk clock, which is obviously not the result of our previous analysis. In fact, it is executed like this. First of all, it can be understood as follows: 1. Non-blocking assignment is assigned after the end of the always block. My personal understanding is that the program assigns values only after seeing the end mark of the always block. However, it does not mean that when the program first sees the statement, there is no action. Instead, the following value is calculated and temporarily stored in a register, and the value is assigned at the end of the block. For example, count+1 is calculated first in the above, and the result is assigned to count at the end of the block. 2. Non-blocking assignment is executed in parallel, so no matter how many always blocks there are, no matter how many non-blocking assignments there are in each always block, they are all executed in parallel at the same time without interfering with each other. So the above program is easy to analyze The initial value of Count is 0. When the rising edge of the first clock arrives, count<=count+1. This statement does not assign a value first (as mentioned earlier, the value is assigned only when the block ends), but count+1 has been calculated and stored in the register. The if statement is executed first. The condition of the if statement is still (count=0) at this time. The condition is false, and the statement inside the if statement is not executed. Then the always block end marker end is encountered, and the assignment of count<= is executed. Count is 1 at this time. Then the second clock rising edge arrives, and the if statement is executed first. The condition is still false, and then count is incremented by 1, and count becomes 2. The third clock rising edge arrives, and the if statement is executed first. The condition is met. As for the three non-blocking assignment statements at this time, count<=count+1; data_a<=!data_a; count<=0; The three statements are logically executed in parallel, but two of them assign values to count at the same time. So what should we do? I am not clear about this yet. I beg experts to explain it, or I will figure it out later and then look at it. On July 25, after Long Ge’s advice, the above problem finally had a reasonable explanation. After referring to many materials, we can conclude that the non-blocking assignment in begin...end is actually sequential execution in parallel. The understanding of this is that the non-blocking assignment statements in the begin...end statement block are parallel to the non-blocking assignment statements in other blocks, but the statements in a single begin...end block are executed sequentially. Therefore, in the Verilog language, it is not allowed to assign values to the same variable in two blocks. In a single block, if two or more non-blocking statements assign values to the same variable, the value of the variable is determined by the last statement.