MSP430(F5529) UCS configuration explanation

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MSP430(F5529) UCS configuration explanation [Copy link]

The UCS of the MSP430F5XX/MSP430F6XX series devices contains five clock sources, namely: XT1CLK, VLOCLK, REFOCLK, DCOCLK and XT2CLK. For a detailed introduction to these five clocks, please refer to the instruction manual of the chip series. Among them, XT1CLK, VLOCLK, REFOCLK and XT2CLK are not much different from the MSP430F1XX series, and they are also relatively simple to learn and configure. After the UCS power-on default state PUC, the default state of the UCS module is as follows: (1) XT1 is in LF mode as the XT1CLK clock source. ACLK is selected as XT1CLK. (2) MCLK is selected as DCOCLKDIV (3) SMCLK is selected as DCOCLKDIV (4) FLL is enabled, and XT1CLK is used as the FLL reference clock. (5) The XIN and XOUT pins are set to general IO. Before XIN and XOUT are configured as XT1 functions, XT1 remains disabled. (6) If available, XT2IN and XT2OUT are set to general purpose IO and remain disabled. It is very important to understand the default state of UCS power-on, which is very important for understanding the subsequent configuration logic. UCS clock source switching Since REFOCLK, VLOCLK, and DCOCLK (here we temporarily assume this) are available in the default state, when switching, you only need to configure the clock sources of ACLK, SMCLK, and MCLK through UCSCTL4, while XT1CLK and XT2CLK need to be determined according to the specific configuration of the hardware. Therefore, the configuration of these two is somewhat different from the first three. Next, we will do three experiments: (1) Configure MCLK and SMCLK with REFOCLK and VLOCLK REFOCLK and VLOCLK are provided by the chip by default. As long as the chip works normally, these two clocks will work normally. Therefore, the clock configuration is very simple. You only need to modify UCSCTL4 and configure SELS and SELM to the corresponding options VLOCLK or REFOCLK. The specific code is as follows: [cpp] view plain copy #include  


void main(void) { WDTCTL = WDTPW+WDTHOLD; P1SEL |= BIT0; P1DIR |= BIT0; //Measure ACLK P2SEL |= BIT2; P2DIR |= BIT2; //Measure SMCLK P7SEL |= BIT7; P7DIR |= BIT7; //Measure MCLK //UCSCTL4 = UCSCTL4&(~(SELS_7|SELM_7))|SELS_1|SELM_1; //Configure SMCLK and MCLK as VLOCLK UCSCTL4 = UCSCTL4&(~(SELS_7|SELM_7))|SELS_2|SELM_2; //Configure SMCLK and MCLK as REFOCLK while(1); } The above code implements the switching of SMCLK and MCLK to VLOCLK and REFOCLK. The operation of ACLK is the same and will not be explained in detail. (2) Configure MCLK and SMCLK as XT1CLK. The development board XT1 I have is connected to a 32.768K watch clock crystal. The configuration of XT1CLK is divided into the following steps: 1. Configure IO ports 5.4 and 5.5 as XT1 functions. 2. Configure XCAP to XCAP_3, which is a 12PF capacitor. 3. Clear the XT1OFF flag. 4. Wait for XT1 to start oscillating. The specific code is as follows: #include  

void main(void) { WDTCTL = WDTPW+WDTHOLD; P1SEL |= BIT0; P1DIR |= BIT0; //Measure ACLK with P2SEL |= BIT2; P2DIR |= BIT2; //Measure SMCLK with P7SEL |= BIT7; P7DIR |= BIT7; //Measure MCLK with P5SEL |= BIT4|BIT5; //Configure IO as XT1 function UCSCTL6 |= XCAP_3; //Configure capacitor to 12pF UCSCTL6 &= ~XT1OFF; //Enable XT1 while (SFRIFG1 & OFIFG){ UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG); // Clear three types of clock flags // Here you need to clear three flags because any // flag will set OFIFG SFRIFG1 &= ~OFIFG; // Clear the clock error flag} UCSCTL4 = UCSCTL4&(~(SELS_7|SELM_7))|SELS_0|SELM_0; //Configure the SMCLK and MCLK clock sources to XT1 while(1); } (3) Configure SMCLK and MCLK to XT2 The process of configuring SMCLK and MCLK to XT2 is basically the same as that of configuring them to XT1. The only difference is that before configuring SMCLK and MCLK to XT2, the clock sources of ACLK and REFCLK need to be changed. Because the default clock source of ACLK and REFCLK is XT1, and we have not configured to start XT1CLK here, an XT1 clock error, namely XT1LFFG, will occur. Therefore, we first configure ACLK and REFCLK to the chip's own clock (REFOCLK or VLOCLK) or the clock to be started (XT2). In addition, there is no need to configure capacitors when configuring XT2, so the code for configuring SMCLK and MCLK to XT2 is as follows: [cpp] view plain copy #include  

void main(void) { WDTCTL = WDTPW+WDTHOLD; P1SEL |= BIT0; P1DIR |= BIT0; //Measure ACLK with P2SEL |= BIT2; P2DIR |= BIT2; //Measure SMCLK with P7SEL |= BIT7; P7DIR |= BIT7; //Measure MCLK with P5SEL |= BIT2|BIT3; //Configure IO as XT2 function UCSCTL6 &= ~XT2OFF; //Enable XT2 UCSCTL4 = UCSCTL4&(~(SELA_7))|SELA_1; //Configure ACLK as VLOCLK first UCSCTL3 |= SELREF_2; //Configure REFCLK as REFCLK while (SFRIFG1 & OFIFG){ UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG); // Clear three types of clock flags // Here we need to clear three types of flags, because any of the // flags will set OFIFG SFRIFG1 &= ~OFIFG; // Clear clock error flag } UCSCTL4 = UCSCTL4&(~(SELS_7|SELM_7))|SELS_5|SELM_5; // Configure SMCLK and MCLK clock sources to XT2 while(1); } After completing the previous three experiments, we can master the basic operations of MSP430F5XX series clock switching.