A brief summary of the operating instructions: (The following is basically nonsense, just understand it)

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A brief summary of the operating instructions: (The following is basically nonsense, just understand it) [Copy link]

MSP430F5529 has multiple clock sources, and the clock sources of many modules can be freely selected. In addition, because in general, system power consumption is proportional to the operating frequency, sometimes by selecting a lower frequency clock source, under normal working conditions, it is possible to effectively reduce power consumption. Although the function library HAL_UCS.c/h has complete control functions, I think it is simpler to operate the registers directly for this chapter because the functions are too short and there are too many of them. 3.1 Introduction to Unified Clock System (UCS) Unified Clock System, UCS. Reasonable configuration of the clock can achieve the purpose of balancing the system and reducing power consumption. The MSPF5529 clock system includes 5 clock sources: ①LFXT1 external low-frequency oscillator source, 32.768KHZ, can be used as the reference source of FLL; ②XT2 external high-frequency oscillator source, 4MHZ; ③VLO (Internal very low) internal low-power low-frequency oscillator source, typically 10KHZ, with average accuracy; ④REFO internal low-frequency reference source, 32.768KHZ, often used as the reference frequency of the phase-locked loop FLL, with high accuracy and no power consumption when not in use. Its setting often refers to the setting of LPM mode; ⑤DCO (Internal digitally-controlled) Internal digitally controlled oscillator source, usually set by FLL; (very useful, very important, will be discussed in detail later) Usually use 3 clock signals, all of which come from the above 5 signal sources: ①ACLK (Auxiliary clock) Auxiliary clock, its clock source can be selected from XT1, REFOC, VLO, DCO, DCOCLKDIV, XT2 by software control. Among them, DCOCLKDIV is obtained by dividing DCO by 1, 2, 4, 8, 16 or 32. Note that ACLK can also be divided by 1, 2, 4, 8, 16 or 32 again. ②MCLK (Master clock) Master clock, its characteristics are exactly the same as ACLK. ③SMCLK (Subsystem master clock): subsystem clock, its characteristics are exactly the same as ACLK. 3.2 UCS Operation Instructions The default clock conditions when powering on are as follows (must be remembered clearly!!!): ACLK: XT1 (when invalid, the low-frequency mode switches to REFO, and switches to DCO in other cases) MCLK: DCOCLKDIV SMCLK: DCOCLKDIV In addition, the reference source of FLL defaults to XT1; If the pins connecting XT1 and XT2 are not set with PXSEL, then these two clock sources are invalid; REFOCLK, VLOCLK, and DCOCLK are available by default; After the system is stable, DCOCLK defaults to 2.097152MHZ, and FLL defaults to 2-division, so the frequencies of MCLK and SMCLK are both 1.048576MHZ. (How to calculate will be mentioned in Experiment 3) In addition, the selection of system reset and system working mode LPM will have a certain impact on UCS. There are too many restrictions here. For details, please refer to the UCS section of TI official data. LPM and system reset will be discussed in the next chapter. ①The choice of VLO is the simplest, and there is no need to consider other situations; ②The selection of REFO needs to refer to different working modes and has various restrictions; ③XT1 and XT2 have the same characteristics. When using, not only the pins connected to it but also the capacitors should be configured, and it should be noted whether it works in low-frequency or high-frequency mode. Moreover, there are different requirements in different working modes; ④DCO is a digitally controlled oscillator, and its frequency can be adjusted not only by itself but also by the FLL phase-locked loop; ⑤FLL phase-locked loop is a flexible choice for frequency conversion. It can set the reference frequency, select the frequency division number, and can be directly turned off to achieve the purpose of reducing power consumption; ⑥ The UCS system has a clock signal error protection mechanism; ⑦ For places with strict timing requirements, it is necessary to select a high-precision clock source and make good modulation settings for the FLL and DCO parts;