Design of a rail-to-rail input low voltage and low power operational amplifier

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Design of a rail-to-rail input low voltage and low power operational amplifier [Copy link]

Author: Jia Zhengya, Zhang Liyan, Huang Yunchuan
This paper uses a 0.35mm CMOS standard process to design a low-voltage and low-power operational amplifier with rail-to-rail input, static power consumption of 150mW, phase gain of 86dB, and unity gain bandwidth of 2.3MHz. The operational amplifier has an almost constant transconductance under common-mode input level, making frequency compensation easier to achieve, and can be applied to VLSI library cells and related technical fields.
Keywords : low power consumption; rail-to-rail; constant transconductance

introduction

　　　As the power supply voltage decreases, the threshold voltage of the transistor does not decrease, but the common-mode input range of the op amp becomes smaller and smaller, which makes it necessary to design an op amp that meets the requirements of low voltage and low power consumption and has a full swing input dynamic amplitude. The low-voltage and low-power CMOS operational amplifier circuit with rail-to-rail (RR) input function designed in this paper has an almost constant transconductance under various common-mode input levels, making frequency compensation easier to achieve, and is suitable for application in VLSI library cells and related technical fields.

Theoretical Model

Basic rail-to-rail input structure

　　　At lower power supply voltages, the input stage design of the operational amplifier is very important. The common-mode input voltage range V CM of a traditional PMOS differential input stage can be expressed as :

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　　Where V SS is the negative power supply voltage, V CM is the common-mode input voltage, V Dsat is the source-drain saturation voltage drop, and V GSP is the gate-source voltage of the PMOS . Similarly, the common-mode input voltage range of the NMOS differential input stage can be expressed as:

740)this.width=740" border=undefined> (2)

　　Where V GSN is the gate-source voltage of NMOS . If the PMOS and NMOS differential pairs are connected in complementary fashion, the input common-mode range of the op amp can be changed to:

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Thus, rail-to-rail common-mode input is achieved. Figure 1 is a circuit diagram of a rail-to-rail input structure.

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Figure 1 Basic rail-to-rail input circuit Figure 2 Low voltage and low power operational amplifier circuit

Transconductance constant structure

　　　The rail-to-rail input stage circuit shown in Figure 1 adopts a complementary folded structure, which allows the common-mode input voltage to work in the entire range from ground to the power supply voltage. If the input stage works in the saturation region, the transconductance of the circuit is determined by the following formula:
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or

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　　Where m n and m p represent the mobility of NMOS and PMOS respectively . As can be seen from the above formula, the transconductance of the input stage will change with the change of gate-source voltage and standby current. Therefore, when the common-mode input level changes from V DD to V SS , the transconductance of the rail-to-rail input differential pair changes from the transconductance of the PMOS differential pair to the sum of the transconductance of the PMOS + NMOS differential pair, and then changes to the transconductance of the NMOS differential pair. The transconductance g m of the middle part is almost twice that of the other parts. This change in transconductance will change the gain error of the op amp, thereby deteriorating the frequency characteristics. Therefore, it is necessary to design a circuit that makes the rail-to-rail input circuit have a constant transconductance.

　　　At present, there are several design methods that can ensure that the gm of the RR input stage is constant: 1. Use a bipolar (BJT) linear complementary differential pair input stage. 2. Use a Zener diode to connect the bias currents of the P and N differential pairs. 3. Use redundant differential pairs to achieve this. 4. Use current mirror technology to make the bias current change with the input common-mode voltage.

The circuit of the fourth method mentioned above is not only simple in structure, but also easy to implement in controlling g m . Therefore, this paper applies the control principle of input transconductance and adopts a new circuit structure to keep the RR input stage g m constant.

Circuit Design

　　　The circuit designed in this paper is shown in Figure 2. The circuit consists of an input complementary differential pair, a constant gm circuit, and a common source and common gate summing circuit. M1 ~ M4 constitute an input complementary differential pair. When the common mode input is low, the P input differential pair M1 and M4 are in working state, the N input differential pair M2 and M3 are cut off, the switch tubes M17 and M18 are turned on , and the current on M16 is extracted ; M13 and M14 are cut off . The current of M15 flows into the P differential pair , and the equivalent differential transconductance of this interval is :

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　　　When the common-mode input voltage is near the middle value, the P differential pair M1 , M4 and the N differential pair M2 , M3 are all turned on, and the control switches M17 , M18 , M13 , and M14 are turned on , and their gate voltages are adjusted respectively so that 3/4 of the current is drawn from M15 and M16 . The equivalent differential transconductance in this interval is :

740)this.width=740" border=undefined> (6)

　　　When in the high common mode input region, the N differential pair M2 and M3 work , and the P differential pair M1 and M4 are turned off. The switch tubes M13 and M14 are turned on, drawing the current on M15 , and the switch tubes M17 and M18 are turned off . The current of M16 flows into the N differential pair . The equivalent differential transconductance in this interval is :

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　　　From the above analysis, we can see that as long as the length-to-width ratio of the four input tubes is reasonably selected, the following relationship is satisfied:

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g m will remain constant.　　

　　　M5 ~ M12 is a common source and common gate summing circuit. The output impedance and voltage gain of this structure are relatively high, and it has good frequency characteristics and power supply rejection ratio. After analysis, it can be seen that when the circuit structure works alternately in a complementary differential pair, when M1 , M4 and M2 , M3 cannot be in saturation at the same time, the static current of the summing circuit M5 ~ M12 changes , causing the output resistance and pole of the circuit to change slightly, which may cause a large transconductance spike in the transition zone. However, since this transition zone is very narrow, it is estimated that such a large spike will not appear, and the input transconductance remains basically constant in the entire common mode range.

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Figure 3 Transconductance simulation results of op amp

Simulation Results

　　　This paper uses the HSpice parameter model of TSMC 's 0.35 mm process device for simulation and obtains the following results. Figure 3 is the total transconductance of the op amp. It can be seen from the figure that when the common-mode input voltage changes from 0V to 2V , the entire transconductance changes within 5% . The change in transconductance in the middle is caused by the change in static current when the differential pair works alternately, as described above.

Conclusion

　　　The operational amplifier designed in this paper has a power supply voltage of 2V , a power consumption of 150mW and a phase margin of 75 °. In the entire common mode range , the transconductance of the input stage remains basically constant, which improves the performance index of the operational amplifier. And the structure is simple, which is particularly suitable as a VLSI library unit.