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Location:
Training
/
Circuit Fundamentals
/
Soc Design Lab - NYCU 2023
/
Verilog
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Playlist
Chapters
Chapter 1:Course plan
Chapter 2:HLS
Chapter 3:Verilog
Chapter 4:Lab3 workbook explained
Chapter 5:verilog delay
Chapter 6:verilog fsm
Chapter 7:Caravel SoC - w4
Chapter 8:Single cycle Processor
Chapter 9:Multicycle processor
Chapter 10:Lab3&4 explanation
Chapter 11:Timer & DMA
Chapter 12:Interrupt
Chapter 13:GPIO
Chapter 14:FSIC
Chapter 15:Interconnect AXI
Chapter 16:Interconnect IO Cache access
Chapter 17:AXI Bus Optimization
Chapter 18:Lab3 review & Lab5
Chapter 19:Memory - Cache
Chapter 20:DRAM
Chapter 21:Memory Tech
Chapter 22:Interrupt
Chapter 23:Synchronization & semaphores
Chapter 24:Explanation
Chapter 25:code review Part 1
Chapter 26:code review Part 2
Chapter 27:SDRAM Explanation
Chapter 28:Performance Optimization
Chapter 29:Final Project - Group 1
Chapter 30:Final Project - Group 2
Chapter 31:Final Project - Group 3
Chapter 32:Final Project - Group 4
Chapter 33:Final Project - Group 5
Chapter 34:Final Project - Group 6
Chapter 35:Final Project - Group 7
Chapter 36:Final Project - Group 8
Chapter 37:Final Project - Group 10
Chapter 38:Final Project - Group 11
Chapter 39:Final Project - Group 12
Chapter 40:Final Project - Group 13
Chapter 41:Final Project - Group 15
Duration:3 hours and 4 minutes and 49 seconds
Date:2024/10/20
Uploader:宋元浩
Introduction
keywords:
SoC
NYCU SOC class recording
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